Start work on schematics
This commit is contained in:
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# OSH Park-compatible 2 Layer KiCad Template
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This is a KiCad template to simplify making printed circuit boards.
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It comes with all the design rules to meet the 2-layer OSH Park specs and stackup.
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- <a href="http://docs.oshpark.com/services/two-layer/">OSH Park Two Layer Specs</a>
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- <a href="http://docs.oshpark.com/design-tools/kicad">OSH Park KiCad help</a>
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### Instructions
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1. Open KiCad.
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1. Open Preferences > Configure Paths and note the value of 'KICAD_PTEMPLATES'.
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1. In KiCad, open File > New Project > New Project from Template.
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1. Select the location of your new project. The name of the folder will be the name of your project.
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1. The templates with folders in the 'KICAD_PTEMPLATES' are listed under 'Portable Templates" tab.
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1. Select the template and click 'OK'.
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1. Your project now exists, so you can open EESchema and PCBNew and design as usual.
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EESchema-DOCLIB Version 2.0
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#
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$CMP ADF4360-7BCPZRL7
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D Phase Locked Loops - PLL Intg Integer-N VCO Out Freq 350-1800
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$ENDCMP
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#
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$CMP HHM17147A1
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D Signal Conditioning Multilyer Balun 673-2700MHz 100 ohms
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$ENDCMP
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#
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#End Doc Library
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EESchema-DOCLIB Version 2.0
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#
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$CMP ADF4360-7BCPZRL7
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D Phase Locked Loops - PLL Intg Integer-N VCO Out Freq 350-1800
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$ENDCMP
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#
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$CMP HHM17147A1
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D Signal Conditioning Multilyer Balun 673-2700MHz 100 ohms
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$ENDCMP
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#
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#End Doc Library
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# ADF4360-7BCPZRL7
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#
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DEF ADF4360-7BCPZRL7 U 0 40 Y Y 1 F N
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F0 "U" 0 450 50 H V C CNN
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F1 "ADF4360-7BCPZRL7" 0 300 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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ALIAS ADF4360-7BCPZ ADF4360-7BCPZRL
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DRAW
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S -700 400 700 -1300 0 1 0 f
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X CPGND 1 550 -1400 100 U 50 50 1 1 P
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X L2 10 -800 -800 100 R 50 50 1 1 P
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X AGND 11 100 -1400 100 U 50 50 1 1 P
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X CC 12 -800 -900 100 R 50 50 1 1 P
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X RSET 13 -800 -1000 100 R 50 50 1 1 P
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X CN 14 -800 -1100 100 R 50 50 1 1 P
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X DGND 15 -300 -1400 100 U 50 50 1 1 P
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X REFIN 16 -800 100 100 R 50 50 1 1 I
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X CLK 17 -800 -50 100 R 50 50 1 1 I
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X DATA 18 -800 -150 100 R 50 50 1 1 I
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X LE 19 -800 -250 100 R 50 50 1 1 I
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X AVDD 2 800 250 100 L 50 50 1 1 W
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X MUXOUT 20 -800 -400 100 R 50 50 1 1 O
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X DVDD 21 -800 250 100 R 50 50 1 1 W
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X AGND 22 200 -1400 100 U 50 50 1 1 P
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X CE 23 -800 -550 100 R 50 50 1 1 I
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X AGND 3 -100 -1400 100 U 50 50 1 1 P
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X RFOUTA 4 800 100 100 L 50 50 1 1 O
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X RFOUTB 5 800 0 100 L 50 50 1 1 O
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X VVCO 6 800 -300 100 L 50 50 1 1 W
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X VTUNE 7 800 -400 100 L 50 50 1 1 I
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X AGND 8 0 -1400 100 U 50 50 1 1 P
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X L1 9 -800 -700 100 R 50 50 1 1 P
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X 24 CP 800 -850 100 L 50 50 1 1 O
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X 25 EP 400 -1400 100 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# HHM17147A1
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#
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DEF HHM17147A1 U 0 40 Y N 1 F N
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F0 "U" 0 0 50 H V C CNN
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F1 "HHM17147A1" 0 -500 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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A -50 -375 25 -899 899 0 1 0 N -50 -400 -50 -350
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A -50 -325 25 -899 899 0 1 0 N -50 -350 -50 -300
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A -50 -275 25 -899 899 0 1 0 N -50 -300 -50 -250
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A -50 -225 25 -899 899 0 1 0 N -50 -250 -50 -200
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A -50 -175 25 -899 899 0 1 0 N -50 -200 -50 -150
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A -50 -125 25 -899 899 0 1 0 N -50 -150 -50 -100
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A 50 -375 25 901 -901 0 1 0 N 50 -350 50 -400
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A 50 -325 25 901 -901 0 1 0 N 50 -300 50 -350
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A 50 -275 25 901 -901 0 1 0 N 50 -250 50 -300
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A 50 -225 25 901 -901 0 1 0 N 50 -200 50 -250
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A 50 -175 25 901 -901 0 1 0 N 50 -150 50 -200
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A 50 -125 25 901 -901 0 1 0 N 50 -100 50 -150
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X SINGLE 1 150 -100 100 L 50 50 1 1 P
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X COMMON 2 -150 -250 100 R 50 50 1 1 P
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X + 3 -150 -100 100 R 50 50 1 1 P
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X - 4 -150 -400 100 R 50 50 1 1 P
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X GND 5 150 -400 100 L 50 50 1 1 P
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X NC 6 150 -250 100 L 50 50 1 1 N N
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ENDDRAW
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ENDDEF
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#
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# Q_NPN_BCEE
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#
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DEF Q_NPN_BCEE Q 0 40 Y N 1 F N
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F0 "Q" 300 0 50 H V C CNN
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F1 "Q_NPN_BCEE" 200 -100 50 H V L CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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C 0 0 111 1 1 10 N
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P 2 1 1 0 -25 25 50 100 N
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P 2 1 1 0 50 -100 150 -100 N
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P 3 1 1 0 -25 -25 50 -100 50 -100 N
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P 3 1 1 20 -25 75 -25 -75 -25 -75 N
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P 5 1 1 0 0 -70 20 -50 40 -90 0 -70 0 -70 F
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X B 1 -250 0 225 R 50 50 1 1 I
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X C 2 50 200 100 D 50 50 1 1 P
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X E 3 50 -200 100 U 50 50 1 1 P
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X C 4 150 -200 100 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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#End Library
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EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# Connector_Conn_Coaxial
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#
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DEF Connector_Conn_Coaxial J 0 40 Y N 1 F N
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F0 "J" 10 120 50 H V C CNN
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F1 "Connector_Conn_Coaxial" 115 0 50 V V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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*BNC*
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*SMA*
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*SMB*
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*SMC*
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*Cinch*
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$ENDFPLIST
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DRAW
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A -2 0 71 1636 0 0 1 10 N -70 20 70 0
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A -1 0 71 0 -1638 0 1 10 N 70 0 -70 -20
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C 0 0 20 0 1 8 N
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P 2 0 1 0 -100 0 -20 0 N
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P 2 0 1 0 0 -100 0 -70 N
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X In 1 -200 0 100 R 50 50 1 1 P
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X Ext 2 0 -200 100 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_C_Small
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#
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DEF Device_C_Small C 0 10 N N 1 F N
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F0 "C" 10 70 50 H V L CNN
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F1 "Device_C_Small" 10 -80 50 H V L CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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C_*
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$ENDFPLIST
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DRAW
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P 2 0 1 13 -60 -20 60 -20 N
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P 2 0 1 12 -60 20 60 20 N
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X ~ 1 0 100 80 D 50 50 1 1 P
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X ~ 2 0 -100 80 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_L_Small
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#
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DEF Device_L_Small L 0 10 N N 1 F N
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F0 "L" 30 40 50 H V L CNN
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F1 "Device_L_Small" 30 -40 50 H V L CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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Choke_*
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*Coil*
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Inductor_*
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L_*
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$ENDFPLIST
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DRAW
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A 0 -60 20 -899 899 0 1 0 N 0 -80 0 -40
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A 0 -20 20 -899 899 0 1 0 N 0 -40 0 0
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A 0 20 20 -899 899 0 1 0 N 0 0 0 40
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A 0 60 20 -899 899 0 1 0 N 0 40 0 80
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X ~ 1 0 100 20 D 50 50 1 1 P
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X ~ 2 0 -100 20 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_R_Small
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#
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DEF Device_R_Small R 0 10 N N 1 F N
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F0 "R" 30 20 50 H V L CNN
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F1 "Device_R_Small" 30 -40 50 H V L CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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R_*
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$ENDFPLIST
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DRAW
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S -30 70 30 -70 0 1 8 N
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X ~ 1 0 100 30 D 50 50 1 1 P
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X ~ 2 0 -100 30 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# discrete-parts_ADF4360-7BCPZRL7
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#
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DEF discrete-parts_ADF4360-7BCPZRL7 U 0 40 Y Y 1 F N
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F0 "U" 0 450 50 H V C CNN
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F1 "discrete-parts_ADF4360-7BCPZRL7" 0 300 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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ALIAS ADF4360-7BCPZ ADF4360-7BCPZRL
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DRAW
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S -700 400 700 -1300 0 1 0 f
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X CPGND 1 550 -1400 100 U 50 50 1 1 P
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X L2 10 -800 -800 100 R 50 50 1 1 P
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X AGND 11 100 -1400 100 U 50 50 1 1 P
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X CC 12 -800 -900 100 R 50 50 1 1 P
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X RSET 13 -800 -1000 100 R 50 50 1 1 P
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X CN 14 -800 -1100 100 R 50 50 1 1 P
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X DGND 15 -300 -1400 100 U 50 50 1 1 P
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X REFIN 16 -800 100 100 R 50 50 1 1 I
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X CLK 17 -800 -50 100 R 50 50 1 1 I
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X DATA 18 -800 -150 100 R 50 50 1 1 I
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X LE 19 -800 -250 100 R 50 50 1 1 I
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X AVDD 2 800 250 100 L 50 50 1 1 W
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X MUXOUT 20 -800 -400 100 R 50 50 1 1 O
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X DVDD 21 -800 250 100 R 50 50 1 1 W
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X AGND 22 200 -1400 100 U 50 50 1 1 P
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X CE 23 -800 -550 100 R 50 50 1 1 I
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X AGND 3 -100 -1400 100 U 50 50 1 1 P
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X RFOUTA 4 800 100 100 L 50 50 1 1 O
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X RFOUTB 5 800 0 100 L 50 50 1 1 O
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X VVCO 6 800 -300 100 L 50 50 1 1 W
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X VTUNE 7 800 -400 100 L 50 50 1 1 I
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X AGND 8 0 -1400 100 U 50 50 1 1 P
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X L1 9 -800 -700 100 R 50 50 1 1 P
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X 24 CP 800 -850 100 L 50 50 1 1 O
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X 25 EP 400 -1400 100 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# discrete-parts_HHM17147A1
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#
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DEF discrete-parts_HHM17147A1 U 0 40 Y N 1 F N
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F0 "U" 0 0 50 H V C CNN
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F1 "discrete-parts_HHM17147A1" 0 -500 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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A -50 -375 25 -899 899 0 1 0 N -50 -400 -50 -350
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A -50 -325 25 -899 899 0 1 0 N -50 -350 -50 -300
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A -50 -275 25 -899 899 0 1 0 N -50 -300 -50 -250
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A -50 -225 25 -899 899 0 1 0 N -50 -250 -50 -200
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A -50 -175 25 -899 899 0 1 0 N -50 -200 -50 -150
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A -50 -125 25 -899 899 0 1 0 N -50 -150 -50 -100
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A 50 -375 25 901 -901 0 1 0 N 50 -350 50 -400
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A 50 -325 25 901 -901 0 1 0 N 50 -300 50 -350
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A 50 -275 25 901 -901 0 1 0 N 50 -250 50 -300
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A 50 -225 25 901 -901 0 1 0 N 50 -200 50 -250
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A 50 -175 25 901 -901 0 1 0 N 50 -150 50 -200
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A 50 -125 25 901 -901 0 1 0 N 50 -100 50 -150
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X SINGLE 1 150 -100 100 L 50 50 1 1 P
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X COMMON 2 -150 -250 100 R 50 50 1 1 P
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X + 3 -150 -100 100 R 50 50 1 1 P
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X - 4 -150 -400 100 R 50 50 1 1 P
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X GND 5 150 -400 100 L 50 50 1 1 P
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X NC 6 150 -250 100 L 50 50 1 1 N N
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ENDDRAW
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ENDDEF
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#
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# discrete-parts_Q_NPN_BCEE
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#
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DEF discrete-parts_Q_NPN_BCEE Q 0 40 Y N 1 F N
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F0 "Q" 300 0 50 H V C CNN
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F1 "discrete-parts_Q_NPN_BCEE" 200 -100 50 H V L CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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C 0 0 111 1 1 10 N
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P 2 1 1 0 -25 25 50 100 N
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P 2 1 1 0 50 -100 150 -100 N
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P 3 1 1 0 -25 -25 50 -100 50 -100 N
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P 3 1 1 20 -25 75 -25 -75 -25 -75 N
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P 5 1 1 0 0 -70 20 -50 40 -90 0 -70 0 -70 F
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X B 1 -250 0 225 R 50 50 1 1 I
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X C 2 50 200 100 D 50 50 1 1 P
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X E 3 50 -200 100 U 50 50 1 1 P
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X C 4 150 -200 100 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# power_GND
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#
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DEF power_GND #PWR 0 0 Y Y 1 F P
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F0 "#PWR" 0 -250 50 H I C CNN
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F1 "power_GND" 0 -150 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
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X GND 1 0 0 0 D 50 50 1 1 W N
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ENDDRAW
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ENDDEF
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#
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#End Library
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EESchema Schematic File Version 4
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LIBS:discrete-rf-board-cache
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EELAYER 26 0
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EELAYER END
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$Descr USLetter 11000 8500
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encoding utf-8
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Sheet 1 4
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Sheet
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S 1825 2725 1775 1550
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U 5CA6B046
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F0 "Local Oscillator" 50
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F1 "lo.sch" 50
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$EndSheet
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$Sheet
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S 5050 1550 1500 1350
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U 5CA6B0AA
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F0 "Receiver" 50
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F1 "receiver.sch" 50
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$EndSheet
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$Sheet
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S 5100 3650 1700 1550
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U 5CA6B0B3
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F0 "Transmitter" 50
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F1 "transmitter.sch" 50
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$EndSheet
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$EndSCHEMATC
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(kicad_pcb (version 20171130) (host pcbnew 5.0.0)
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(general
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(thickness 1.6)
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(drawings 1)
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(tracks 0)
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(zones 0)
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(modules 0)
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(nets 1)
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)
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||||
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(page USLetter)
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(title_block
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(title "Project Title")
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)
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(layers
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(0 F.Cu signal)
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(31 B.Cu signal)
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(34 B.Paste user)
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(35 F.Paste user)
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(36 B.SilkS user)
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(37 F.SilkS user)
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(38 B.Mask user)
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(39 F.Mask user)
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(40 Dwgs.User user)
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(44 Edge.Cuts user)
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(46 B.CrtYd user)
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(47 F.CrtYd user)
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(48 B.Fab user)
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(49 F.Fab user)
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)
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(setup
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(last_trace_width 0.1524)
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(user_trace_width 0.1524)
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(user_trace_width 0.254)
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(user_trace_width 0.3302)
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(user_trace_width 0.508)
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(user_trace_width 0.762)
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(user_trace_width 1.27)
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(trace_clearance 0.1524)
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(zone_clearance 0.508)
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(zone_45_only no)
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(trace_min 0.1524)
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(segment_width 0.1524)
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(edge_width 0.1524)
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(via_size 0.6858)
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(via_drill 0.3302)
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(via_min_size 0.6858)
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(via_min_drill 0.3302)
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(user_via 0.6858 0.3302)
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(user_via 0.762 0.4064)
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(user_via 0.8636 0.508)
|
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(uvia_size 0.6858)
|
||||
(uvia_drill 0.3302)
|
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(uvias_allowed no)
|
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(uvia_min_size 0)
|
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(uvia_min_drill 0)
|
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(pcb_text_width 0.1524)
|
||||
(pcb_text_size 1.016 1.016)
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(mod_edge_width 0.1524)
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(mod_text_size 1.016 1.016)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(visible_elements FFFEDF7D)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(scaleselection 1)
|
||||
(outputdirectory "gerbers"))
|
||||
)
|
||||
|
||||
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|
||||
|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
|
||||
(gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n5. ROHS COMPLIANCE IS NOT REQUIRED.\n6. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n SOLDER MASK (ANY COLOR) OVER BARE COPPER. \n7. SILK: BOTH SIDES OF THE BOARD SHALL HAVE \n WHITE SILKSCREEN. DO NOT PLACE SILK OVER BARE COPPER.\n8. FINISH: HASL/ENIG.\n9. MINIMUM TRACE WIDTH - 0.006 INCH.\n MINIMUM SPACE - 0.006 INCH.\n MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 113.4872 93.2688) (layer Dwgs.User)
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)
|
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|
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)
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
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|
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||||
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||||
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||||
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||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(48 B.Fab user)
|
||||
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|
||||
)
|
||||
|
||||
(setup
|
||||
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|
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(outputdirectory "gerbers"))
|
||||
)
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(net 0 "")
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(net_class Default "This is the default net class."
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(clearance 0.1524)
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|
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(gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n5. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n SOLDER MASK (ANY COLOR) OVER BARE COPPER. \n6. SILK: BOTH SIDES OF THE BOARD SHALL HAVE \n WHITE SILKSCREEN. DO NOT PLACE SILK OVER BARE COPPER.\n7. FINISH: HASL/ENIG.\n8. MINIMUM TRACE WIDTH - 0.006 INCH.\n MINIMUM SPACE - 0.006 INCH.\n MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 113.4872 93.2688) (layer Dwgs.User)
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(effects (font (size 2.54 2.54) (thickness 0.254)) (justify left))
|
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)
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|
||||
)
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
update=Tue 11 Oct 2016 05:25:07 PM PDT
|
||||
version=1
|
||||
last_client=kicad
|
||||
[cvpcb]
|
||||
version=1
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||||
NetIExt=net
|
||||
[pcbnew]
|
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version=1
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||||
BoardOutlineThickness=0.152400000000
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||||
ModuleOutlineThickness=0.152400000000
|
||||
[eeschema]
|
||||
version=1
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||||
[eeschema/libraries]
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|
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version=1
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NetFmtName=
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LabSize=50
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[general]
|
||||
version=1
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||||
|
|
@ -0,0 +1,35 @@
|
|||
EESchema Schematic File Version 4
|
||||
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||||
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||||
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|
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||||
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$EndSheet
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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EELAYER 26 0
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$Descr A4 11693 8268
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encoding utf-8
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||||
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|
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$EndDescr
|
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$EndSCHEMATC
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
(sym_lib_table
|
||||
(lib (name discrete-parts)(type Legacy)(uri /home/kelvin/repos/ism-915mhz-transceiver/pcb/discrete/discrete-rf-board/discrete-parts.lib)(options "")(descr ""))
|
||||
)
|
||||
|
|
@ -0,0 +1,17 @@
|
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|
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|
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$EndSCHEMATC
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|
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@ -0,0 +1,17 @@
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|
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$EndDescr
|
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$EndSCHEMATC
|
||||
Loading…
Reference in New Issue