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Fix bugs in ADC debug code; woah that actually workedgit add .

This commit is contained in:
Kelvin Ly 2020-01-08 23:54:54 -05:00
parent 21984a4b1a
commit 31d43b5b71
1 changed files with 7 additions and 6 deletions
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13
rtl/bldc.v
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@ -69,10 +69,10 @@ always @(posedge clk) begin
cur_channel <= adc_vals[cur_idx[3:2]]; cur_channel <= adc_vals[cur_idx[3:2]];
case (cur_idx[1:0]) case (cur_idx[1:0])
2'b00: cur_nibble <= cur_channel[3:0]; 2'b11: cur_nibble <= cur_channel[3:0];
2'b01: cur_nibble <= cur_channel[7:4]; 2'b10: cur_nibble <= cur_channel[7:4];
2'b10: cur_nibble <= cur_channel[11:8]; 2'b01: cur_nibble <= cur_channel[11:8];
2'b11: cur_nibble <= cur_channel[15:12]; 2'b00: cur_nibble <= cur_channel[15:12];
endcase endcase
case (cur_nibble) case (cur_nibble)
@ -110,9 +110,10 @@ always @(posedge clk) begin
end end
if (dbg_tx_rdy) begin if (dbg_tx_rdy) begin
if (uart_bsy) begin if (uart_bsy & ~dbg_buf_vld) begin
if (~uart_end) begin if (~uart_end) begin
// write the ADC data to the UART // write the ADC data to the UART
//dbg_buf <= cur_idx;
dbg_buf <= nibble_hex; dbg_buf <= nibble_hex;
dbg_buf_vld <= 1; dbg_buf_vld <= 1;
@ -121,7 +122,7 @@ always @(posedge clk) begin
uart_end <= 1; uart_end <= 1;
end else begin end else begin
// write newline // write newline
dbg_buf <= 8'h0a; dbg_buf <= 8'h0d;
dbg_buf_vld <= 1; dbg_buf_vld <= 1;
uart_end <= 0; uart_end <= 0;