From 31d43b5b717fc6b4d9ede5b0b05746fadb8dc46b Mon Sep 17 00:00:00 2001
From: Kelvin Ly <kelvin.ly1618@gmail.com>
Date: Wed, 8 Jan 2020 23:54:54 -0500
Subject: [PATCH] Fix bugs in ADC debug code; woah that actually workedgit add
 .

---
 rtl/bldc.v | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/rtl/bldc.v b/rtl/bldc.v
index 9867da2..d8fc1ac 100644
--- a/rtl/bldc.v
+++ b/rtl/bldc.v
@@ -69,10 +69,10 @@ always @(posedge clk) begin
   cur_channel <= adc_vals[cur_idx[3:2]];
 
   case (cur_idx[1:0])
-    2'b00: cur_nibble <= cur_channel[3:0];
-    2'b01: cur_nibble <= cur_channel[7:4];
-    2'b10: cur_nibble <= cur_channel[11:8];
-    2'b11: cur_nibble <= cur_channel[15:12];
+    2'b11: cur_nibble <= cur_channel[3:0];
+    2'b10: cur_nibble <= cur_channel[7:4];
+    2'b01: cur_nibble <= cur_channel[11:8];
+    2'b00: cur_nibble <= cur_channel[15:12];
   endcase
 
   case (cur_nibble)
@@ -110,9 +110,10 @@ always @(posedge clk) begin
   end
 
   if (dbg_tx_rdy) begin
-    if (uart_bsy) begin
+    if (uart_bsy & ~dbg_buf_vld) begin
       if (~uart_end) begin
         // write the ADC data to the UART
+        //dbg_buf <= cur_idx;
         dbg_buf <= nibble_hex;
         dbg_buf_vld <= 1;
 
@@ -121,7 +122,7 @@ always @(posedge clk) begin
           uart_end <= 1;
       end else begin
         // write newline
-        dbg_buf <= 8'h0a;
+        dbg_buf <= 8'h0d;
         dbg_buf_vld <= 1;
 
         uart_end <= 0;