148 lines
2.7 KiB
Verilog
148 lines
2.7 KiB
Verilog
module bldc (
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input clk,
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output dbg_tx,
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output if_int,
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output adc_ss,
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output adc_sck,
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input adc_so,
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output adc_si
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);
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reg [7:0] dbg_buf = 0;
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reg dbg_buf_vld = 0;
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wire dbg_tx_rdy;
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reg [15:0] adc_vals[3:0];
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reg [1:0] vals_idx = 0;
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initial begin
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adc_vals[0] = 0;
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adc_vals[1] = 0;
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adc_vals[2] = 0;
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adc_vals[3] = 0;
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end
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wire [1:0] adc_channel;
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wire [11:0] adc_val;
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wire adc_vld;
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reg adc_ack = 0;
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adc_driver adc0(
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.clk(clk),
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.rstn(1'b1),
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.so(adc_so),
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.si(adc_si),
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.ss(adc_ss),
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.sck(adc_sck),
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.channel(adc_channel),
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.val(adc_val),
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.vld(adc_vld),
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.ack(adc_ack)
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);
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uart_tx_115200 dbg(
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.clk_25mhz(clk),
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.rstn(1'b1),
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.tx(dbg_tx),
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.tx_buf(dbg_buf),
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.vld(dbg_buf_vld),
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.rdy(dbg_tx_rdy)
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);
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reg [7:0] tmp3 = 0;
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reg [7:0] tmp2 = 0;
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reg [7:0] tmp = 0;
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assign if_int = tmp[3];
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reg uart_end = 0;
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reg uart_bsy = 0;
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// stores {cur_channel_idx, cur_nibble}
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reg [3:0] cur_idx = 0;
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reg [15:0] cur_channel;
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reg [3:0] cur_nibble;
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reg [7:0] nibble_hex;
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always @(posedge clk) begin
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cur_channel <= adc_vals[cur_idx[3:2]];
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case (cur_idx[1:0])
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2'b11: cur_nibble <= cur_channel[3:0];
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2'b10: cur_nibble <= cur_channel[7:4];
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2'b01: cur_nibble <= cur_channel[11:8];
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2'b00: cur_nibble <= cur_channel[15:12];
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endcase
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case (cur_nibble)
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4'h0: nibble_hex <= 48;
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4'h1: nibble_hex <= 49;
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4'h2: nibble_hex <= 50;
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4'h3: nibble_hex <= 51;
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4'h4: nibble_hex <= 52;
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4'h5: nibble_hex <= 53;
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4'h6: nibble_hex <= 54;
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4'h7: nibble_hex <= 55;
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4'h8: nibble_hex <= 56;
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4'h9: nibble_hex <= 57;
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4'ha: nibble_hex <= 97;
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4'hb: nibble_hex <= 98;
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4'hc: nibble_hex <= 99;
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4'hd: nibble_hex <= 100;
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4'he: nibble_hex <= 101;
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4'hf: nibble_hex <= 102;
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endcase
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end
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always @(posedge clk) begin
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tmp <= tmp + 1;
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if (&tmp) begin
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tmp2 <= tmp2 + 1;
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if (&tmp2)
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tmp3 <= tmp3 + 1;
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end
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// 25 MHz / 2^(8+8+7) = 3 Hz
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if (&tmp & &tmp2 & &tmp3[6:0]) begin
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uart_bsy <= 1;
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cur_idx <= 0;
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end
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if (dbg_tx_rdy) begin
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if (uart_bsy & ~dbg_buf_vld) begin
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if (~uart_end) begin
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// write the ADC data to the UART
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//dbg_buf <= cur_idx;
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dbg_buf <= nibble_hex;
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dbg_buf_vld <= 1;
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cur_idx <= cur_idx + 1;
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if (&cur_idx)
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uart_end <= 1;
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end else begin
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// write newline
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dbg_buf <= 8'h0d;
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dbg_buf_vld <= 1;
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uart_end <= 0;
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uart_bsy <= 0;
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end
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end
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end else begin
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dbg_buf_vld <= 0;
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end
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if (adc_vld) begin
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adc_ack <= 1;
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vals_idx <= vals_idx + 1;
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if (~uart_bsy) begin
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adc_vals[vals_idx] <= {adc_channel, adc_val};
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end
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end else begin
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adc_ack <= 0;
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end
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end
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endmodule
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