Kelvin Ly 0e67bfc6dc Finish ADC testbench for now TODO check to make sure CS is toggled at the right times		2020-01-07 19:58:48 -05:00
..
library	Finish ADC testbench for now TODO check to make sure CS is toggled at the right times	2020-01-07 19:58:48 -05:00
tb	Finish ADC testbench for now TODO check to make sure CS is toggled at the right times	2020-01-07 19:58:48 -05:00
.gitignore	Get ice timing reporting working	2020-01-05 15:17:28 -05:00
Makefile	Working UART TX!	2020-01-05 16:55:52 -05:00
bldc.pcf	Working UART TX!	2020-01-05 16:55:52 -05:00
bldc.v	Working UART TX!	2020-01-05 16:55:52 -05:00
flash.sh	Mostly working workflow for programming the FPGA	2020-01-05 13:06:33 -05:00
ice40flow	Mostly working workflow for programming the FPGA	2020-01-05 13:06:33 -05:00
ice40flow.env	Mostly working workflow for programming the FPGA	2020-01-05 13:06:33 -05:00
run_yosys.sh	Mostly working workflow for programming the FPGA	2020-01-05 13:06:33 -05:00