Replace rtn with rst, start work on DRV3535 SPI configuration

pcb/bldc-controller.sch

@@ -863,8 +863,6 @@ Wire Wire Line
 	1700 2700 1450 2700
 Wire Wire Line
 	1700 3250 1450 3250
-Wire Wire Line
-	1700 3700 1850 3700
 Wire Wire Line
 	1700 3900 1850 3900
 Text Label 2100 2950 0    50   ~ 0
@@ -3852,10 +3850,6 @@ Wire Wire Line
 	3200 1300 4400 1300
 Text Label 2000 3550 2    50   ~ 0
 VSOURCE
-NoConn ~ 9650 2650
-NoConn ~ 9650 2750
-NoConn ~ 9650 3450
-NoConn ~ 9650 3550
 NoConn ~ 9650 3650
 NoConn ~ 9650 3750
 NoConn ~ 10750 8550
@@ -3989,4 +3983,46 @@ Text Notes 2500 7400 0    50   ~ 0
 TODO fix silkscreen position of C6 and C8
 Text Notes 11800 6450 0    50   ~ 0
 TODO fix routing; SI and SO are backwards\nFLASH_SI = DO\nFLASH_SO = DI
+Text Notes 8150 2900 0    50   ~ 0
+TODO maybe hook up the buck\nregulator output to VM to save on power dissipation
+$Comp
+L power:GND #PWR?
+U 1 1 5E1D5A9A
+P 9450 2650
+F 0 "#PWR?" H 9450 2400 50  0001 C CNN
+F 1 "GND" H 9450 2500 50  0000 C CNN
+F 2 "" H 9450 2650 50  0001 C CNN
+F 3 "" H 9450 2650 50  0001 C CNN
+	1    9450 2650
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	9450 2650 9650 2650
+$Comp
+L power:GND #PWR?
+U 1 1 5E26E530
+P 9450 3550
+F 0 "#PWR?" H 9450 3300 50  0001 C CNN
+F 1 "GND" H 9450 3400 50  0000 C CNN
+F 2 "" H 9450 3550 50  0001 C CNN
+F 3 "" H 9450 3550 50  0001 C CNN
+	1    9450 3550
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	9450 3550 9650 3550
+Text Label 1500 3700 2    50   ~ 0
+SPB
+Text Label 1300 3700 2    50   ~ 0
+SPC
+Wire Wire Line
+	1300 3700 1850 3700
+Text Label 9600 2750 2    50   ~ 0
+SPB
+Wire Wire Line
+	9600 2750 9650 2750
+Text Label 9600 3450 2    50   ~ 0
+SPC
+Wire Wire Line
+	9600 3450 9650 3450
 $EndSCHEMATC

pcb/bldc-controller.sch-bak

@@ -863,8 +863,6 @@ Wire Wire Line
 	1700 2700 1450 2700
 Wire Wire Line
 	1700 3250 1450 3250
-Wire Wire Line
-	1700 3700 1850 3700
 Wire Wire Line
 	1700 3900 1850 3900
 Text Label 2100 2950 0    50   ~ 0
@@ -3852,10 +3850,6 @@ Wire Wire Line
 	3200 1300 4400 1300
 Text Label 2000 3550 2    50   ~ 0
 VSOURCE
-NoConn ~ 9650 2650
-NoConn ~ 9650 2750
-NoConn ~ 9650 3450
-NoConn ~ 9650 3550
 NoConn ~ 9650 3650
 NoConn ~ 9650 3750
 NoConn ~ 10750 8550
@@ -3869,8 +3863,6 @@ Wire Wire Line
 	2700 1800 3200 1800
 Text Label 2100 1800 2    50   ~ 0
 VSOURCE
-Text Notes 10950 4850 0    50   ~ 0
-TODO add connector for programming Flash
 Connection ~ 6600 7650
 Wire Wire Line
 	6600 7650 6600 7950
@@ -3991,4 +3983,48 @@ Text Notes 2500 7400 0    50   ~ 0
 TODO fix silkscreen position of C6 and C8
 Text Notes 11800 6450 0    50   ~ 0
 TODO fix routing; SI and SO are backwards\nFLASH_SI = DO\nFLASH_SO = DI
+Text Notes 8150 2900 0    50   ~ 0
+TODO maybe hook up the buck\nregulator output to VM to save on power dissipation
+Text Notes 8000 4550 0    50   ~ 0
+TODO SPB,SNB,SPC,SNC need to be wired to stuff\nSNx = ground, SPx = positive side of the sense resistor
+$Comp
+L power:GND #PWR?
+U 1 1 5E1D5A9A
+P 9450 2650
+F 0 "#PWR?" H 9450 2400 50  0001 C CNN
+F 1 "GND" H 9450 2500 50  0000 C CNN
+F 2 "" H 9450 2650 50  0001 C CNN
+F 3 "" H 9450 2650 50  0001 C CNN
+	1    9450 2650
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	9450 2650 9650 2650
+$Comp
+L power:GND #PWR?
+U 1 1 5E26E530
+P 9450 3550
+F 0 "#PWR?" H 9450 3300 50  0001 C CNN
+F 1 "GND" H 9450 3400 50  0000 C CNN
+F 2 "" H 9450 3550 50  0001 C CNN
+F 3 "" H 9450 3550 50  0001 C CNN
+	1    9450 3550
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	9450 3550 9650 3550
+Text Label 1500 3700 2    50   ~ 0
+SPB
+Text Label 1300 3700 2    50   ~ 0
+SPC
+Wire Wire Line
+	1300 3700 1850 3700
+Text Label 9600 2750 2    50   ~ 0
+SPB
+Wire Wire Line
+	9600 2750 9650 2750
+Text Label 9600 3450 2    50   ~ 0
+SPC
+Wire Wire Line
+	9600 3450 9650 3450
 $EndSCHEMATC

rtl/bldc.v

@@ -29,7 +29,7 @@ reg adc_ack = 0;
 
 adc_driver adc0(
   .clk(clk),
-  .rstn(1'b1),
+  .rst(1'b0),
   .so(adc_so),
   .si(adc_si),
   .ss(adc_ss),
@@ -43,7 +43,7 @@ adc_driver adc0(
 
 uart_tx_115200 dbg(
   .clk_25mhz(clk),
-  .rstn(1'b1),
+  .rst(1'b0),
   .tx(dbg_tx),
   .tx_buf(dbg_buf),
   .vld(dbg_buf_vld),

rtl/library/adc_driver.v

@@ -7,7 +7,7 @@
 // polls it for new data
 module adc_driver(
   input clk,
-  input rstn,
+  input rst,
 
   input so,
   output si,
@@ -33,7 +33,7 @@ wire strobe = sck_strobe;
 wire strobe2 = ~sck_strobe;
 
 always @(posedge clk) begin
-  if (rstn)
+  if (~rst)
     sck_strobe <= sck_strobe + 1;
   else
     sck_strobe <= 0;
@@ -85,7 +85,7 @@ always @* begin
   ss_next = 1;
   si_next = 0;
 
-  if (rstn) begin
+  if (~rst) begin
     // latch sck and ss state until the strobe happens
     si_next = si;
     ss_next = ss;

rtl/library/drv8353r_driver.v

@@ -0,0 +1,106 @@
+// this module configures the DRV8353,
+// leaving the PWM for a different module
+// if the fault pin is triggered
+// it will read the fault status registers
+// and assert the appropriate output wire
+// it also allows disabling/enabling
+// the MOSFETs using the coast/brake pins
+// in the driver control register
+module drv8353r_driver(
+  input clk,
+  input rst,
+  input en,
+
+  input drv_fault_n,
+  output drv_en,
+
+  output drv_cs_n,
+  output drv_sck,
+  output drv_sdi,
+  output drv_sdo,
+
+  // assert stop with the coast_nbrake
+  // bit to disable the gate drivers
+  input stop,
+  input coast_nbrake,
+  input clear_fault,
+
+  output rdy,
+  output fault_a,
+  output fault_b,
+  output fault_c,
+  );
+
+wire [15:0] driver_control;
+wire [15:0] hs_control;
+wire [15:0] ls_control;
+wire [15:0] ocp_control;
+wire [15:0] csa_control;
+
+assign driver_control = {
+  4'b0010, // address = 0x02
+  1'b1, // write
+  1'b0, // OCP_ACT, shutdown affected half bridge on fault
+  1'b0, // DIS_GDUV, undervoltage enabled
+  1'b0, // DIS_GDF, gate drive fault enabled
+  1'b0, // OTW_REP, overtemp not reported
+  2'b01, // PWM_MODE, 3x PWM mode
+  1'b0, // 1PWM_COM, 1x PWM uses synchronous rectifier
+  1'b0, // 1PWM_DIR, default
+  1'b0, // COAST, disabled
+  1'b0, // BRAKE, disabled
+  1'b0, // CLR_FLT, no clear
+};
+// TODO actually calculate HS/LS gate drive
+// requirements
+assign hs_control = {
+  4'b0011, // address = 0x03
+  1'b1, // write
+  3'b000, // LOCK, don't lock or unlock
+  4'b0100, // IDRIVEP_HS, 300 mA
+  4'b0010, // IDRIVEN_HS, 200 mA
+};
+assign ls_control = {
+  4'b0100, // address = 0x04
+  1'b1, // write
+  1'b1, // CBC, OCP conditions reset when PWM is provided
+  2'b11, // TDRIVE = 4000 ns gate-current drive time
+  4'b0100, // IDRIVEP_LS, 300 mA
+  4'b0010, // IDRIVEN_LS, 200 mA
+};
+assign ocp_control = {
+  4'b0101, // address = 0x05
+  1'b1, // write
+  1'b0, // TRETRY, VDS_OCP/SEN_OCP retry time is 8ms
+  2'b01, // DEAD_TIME, 100 ns deadtime
+  2'b01, // OCP_MODE, overcurrent causes automatic retry
+  2'b10, // OCP_DEG, 4us overcurrent deglitch
+  4'b1101, // VDS_LVL, 1V
+};
+assign csa_control = {
+  4'b0110, // address = 0x06
+  1'b1, // write
+  1'b0, // CSA_FET = SPx
+  1'b0, // VREF_DIV, unidirectional
+  1'b0, // LS_REF, VDS_OCP is measured from SHx to SNx
+  2'b10, // CSA_GAIN, 20V/V
+  1'b0, // DIS_SEN overcurrent fault enabled
+  1'b0, // CSA_CAL_A, normal operation
+  1'b0, // CSA_CAL_B, normal operation
+  1'b0, // CSA_CAL_C, normal operation
+  2'b11, // SEN_LVL, OCP 1 V
+};
+
+reg [3:0] cur_bit;
+wire [4:0] config_bits;
+wire config_bit;
+
+assign config_bits[0] = driver_control[cur_bit];
+assign config_bits[1] = hs_control[cur_bit];
+assign config_bits[2] = ls_control[cur_bit];
+assign config_bits[3] =
+  ocp_control[cur_bit];
+assign config_bits[4] =
+  csa_control[cur_bit];
+
+endmodule

rtl/library/uart_tx_115200.v

@@ -1,6 +1,6 @@
 module uart_tx_115200(
   input clk_25mhz,
-  input rstn,
+  input rst,
   output reg tx,
   input [7:0] tx_buf,
   input vld,
@@ -34,7 +34,7 @@ always @* begin
   counter_next = counter;
   b_next = b;
 
-  if (rstn) begin
+  if (~rst) begin
     if (counter == 216) begin
       counter_next = 0;
       b_next = b + 1;

rtl/tb/adc_driver_tb.v

@@ -3,7 +3,7 @@
 module top();
 
 reg clk = 0;
-reg rstn = 1;
+reg rst = 0;
 reg adc_so = 1;
 wire adc_si;
 wire adc_sck;
@@ -20,7 +20,7 @@ reg ack = 0;
 
 adc_driver dut(
   .clk(clk),
-  .rstn(rstn),
+  .rst(rst),
   .so(adc_so),
   .si(adc_si),
   .ss(adc_ss),
@@ -38,7 +38,7 @@ reg [15:0] out;
 
 initial begin
   clk = 0;
-  rstn = 1;
+  rst = 0;
   adc_so = 1;
   sck_old = 1;