107 lines
2.7 KiB
Verilog
107 lines
2.7 KiB
Verilog
// this module configures the DRV8353,
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// leaving the PWM for a different module
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// if the fault pin is triggered
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// it will read the fault status registers
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// and assert the appropriate output wire
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// it also allows disabling/enabling
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// the MOSFETs using the coast/brake pins
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// in the driver control register
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module drv8353r_driver(
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input clk,
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input rst,
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input en,
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input drv_fault_n,
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output drv_en,
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output drv_cs_n,
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output drv_sck,
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output drv_sdi,
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output drv_sdo,
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// assert stop with the coast_nbrake
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// bit to disable the gate drivers
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input stop,
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input coast_nbrake,
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input clear_fault,
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output rdy,
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output fault_a,
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output fault_b,
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output fault_c,
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);
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wire [15:0] driver_control;
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wire [15:0] hs_control;
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wire [15:0] ls_control;
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wire [15:0] ocp_control;
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wire [15:0] csa_control;
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assign driver_control = {
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4'b0010, // address = 0x02
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1'b1, // write
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1'b0, // OCP_ACT, shutdown affected half bridge on fault
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1'b0, // DIS_GDUV, undervoltage enabled
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1'b0, // DIS_GDF, gate drive fault enabled
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1'b0, // OTW_REP, overtemp not reported
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2'b01, // PWM_MODE, 3x PWM mode
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1'b0, // 1PWM_COM, 1x PWM uses synchronous rectifier
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1'b0, // 1PWM_DIR, default
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1'b0, // COAST, disabled
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1'b0, // BRAKE, disabled
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1'b0, // CLR_FLT, no clear
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};
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// TODO actually calculate HS/LS gate drive
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// requirements
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assign hs_control = {
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4'b0011, // address = 0x03
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1'b1, // write
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3'b000, // LOCK, don't lock or unlock
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4'b0100, // IDRIVEP_HS, 300 mA
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4'b0010, // IDRIVEN_HS, 200 mA
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};
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assign ls_control = {
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4'b0100, // address = 0x04
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1'b1, // write
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1'b1, // CBC, OCP conditions reset when PWM is provided
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2'b11, // TDRIVE = 4000 ns gate-current drive time
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4'b0100, // IDRIVEP_LS, 300 mA
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4'b0010, // IDRIVEN_LS, 200 mA
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};
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assign ocp_control = {
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4'b0101, // address = 0x05
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1'b1, // write
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1'b0, // TRETRY, VDS_OCP/SEN_OCP retry time is 8ms
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2'b01, // DEAD_TIME, 100 ns deadtime
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2'b01, // OCP_MODE, overcurrent causes automatic retry
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2'b10, // OCP_DEG, 4us overcurrent deglitch
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4'b1101, // VDS_LVL, 1V
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};
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assign csa_control = {
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4'b0110, // address = 0x06
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1'b1, // write
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1'b0, // CSA_FET = SPx
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1'b0, // VREF_DIV, unidirectional
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1'b0, // LS_REF, VDS_OCP is measured from SHx to SNx
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2'b10, // CSA_GAIN, 20V/V
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1'b0, // DIS_SEN overcurrent fault enabled
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1'b0, // CSA_CAL_A, normal operation
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1'b0, // CSA_CAL_B, normal operation
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1'b0, // CSA_CAL_C, normal operation
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2'b11, // SEN_LVL, OCP 1 V
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};
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reg [3:0] cur_bit;
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wire [4:0] config_bits;
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wire config_bit;
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assign config_bits[0] = driver_control[cur_bit];
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assign config_bits[1] = hs_control[cur_bit];
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assign config_bits[2] = ls_control[cur_bit];
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assign config_bits[3] =
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ocp_control[cur_bit];
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assign config_bits[4] =
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csa_control[cur_bit];
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endmodule
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