342 lines
13 KiB
C
342 lines
13 KiB
C
/**
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* Copyright (c) 2018 - 2019, Nordic Semiconductor ASA
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic
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* Semiconductor ASA integrated circuit in a product or a software update for
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* such product, must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef NRF_DPPI_H__
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#define NRF_DPPI_H__
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#include <nrfx.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @defgroup nrf_dppi_hal DPPI Controller HAL
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* @{
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* @ingroup nrf_dppi
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* @brief Hardware access layer for managing the Distributed Programmable Peripheral
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* Interconnect Controller (DPPIC).
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*/
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/** @brief DPPI channel groups. */
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typedef enum
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{
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NRF_DPPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
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NRF_DPPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
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NRF_DPPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
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NRF_DPPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
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NRF_DPPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
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NRF_DPPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
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} nrf_dppi_channel_group_t;
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/** @brief DPPI tasks. */
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typedef enum
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{
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NRF_DPPI_TASK_CHG0_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].EN), /**< Enable channel group 0. */
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NRF_DPPI_TASK_CHG0_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].DIS), /**< Disable channel group 0. */
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NRF_DPPI_TASK_CHG1_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].EN), /**< Enable channel group 1. */
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NRF_DPPI_TASK_CHG1_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].DIS), /**< Disable channel group 1. */
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NRF_DPPI_TASK_CHG2_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].EN), /**< Enable channel group 2. */
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NRF_DPPI_TASK_CHG2_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].DIS), /**< Disable channel group 2. */
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NRF_DPPI_TASK_CHG3_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].EN), /**< Enable channel group 3. */
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NRF_DPPI_TASK_CHG3_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].DIS), /**< Disable channel group 3. */
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NRF_DPPI_TASK_CHG4_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].EN), /**< Enable channel group 4. */
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NRF_DPPI_TASK_CHG4_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].DIS), /**< Disable channel group 4. */
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NRF_DPPI_TASK_CHG5_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].EN), /**< Enable channel group 5. */
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NRF_DPPI_TASK_CHG5_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].DIS) /**< Disable channel group 5. */
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} nrf_dppi_task_t;
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/**
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* @brief Function for activating a DPPI task.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] dppi_task Task to be activated.
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*/
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__STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task);
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/**
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* @brief Function for getting the address of the specified DPPI task register.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] task Requested task.
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*
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* @return Address of the specified task register.
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*/
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__STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
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nrf_dppi_task_t task);
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/**
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* @brief Function for checking the state of a specific DPPI channel.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] channel Channel to be checked.
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*
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* @retval true The channel is enabled.
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* @retval false The channel is not enabled.
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*/
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__STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel);
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/**
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* @brief Function for enabling multiple DPPI channels.
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*
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* The bits in @c mask value correspond to particular channels. It means that
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* writing 1 to bit 0 enables channel 0, writing 1 to bit 1 enables channel 1 etc.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] mask Channel mask.
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*/
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__STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask);
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/**
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* @brief Function for disabling multiple DPPI channels.
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*
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* The bits in @c mask value correspond to particular channels. It means that
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* writing 1 to bit 0 disables channel 0, writing 1 to bit 1 disables channel 1 etc.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] mask Channel mask.
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*/
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__STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask);
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/**
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* @brief Function for disabling all DPPI channels.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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*/
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__STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg);
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/**
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* @brief Function for setting the subscribe configuration for a given
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* DPPI task.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] task Task for which to set the configuration.
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* @param[in] channel Channel through which to subscribe events.
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*/
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__STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
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nrf_dppi_task_t task,
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uint8_t channel);
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/**
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* @brief Function for clearing the subscribe configuration for a given
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* DPPI task.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] task Task for which to clear the configuration.
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*/
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__STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task);
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/**
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* @brief Function for including multiple DPPI channels in a channel group.
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*
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* @details This function adds all specified channels to the group.
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* The bits in @p channel_mask value correspond to particular channels. It means that
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* writing 1 to bit 0 includes channel 0, writing 1 to bit 1 includes channel 1 etc.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] channel_mask Channels to be included in the group.
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* @param[in] channel_group Channel group.
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*/
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__STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
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uint32_t channel_mask,
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nrf_dppi_channel_group_t channel_group);
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/**
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* @brief Function for removing multiple DPPI channels from a channel group.
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*
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* @details This function removes all specified channels from the group.
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* The bits in @c channel_mask value correspond to particular channels. It means that
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* writing 1 to bit 0 removes channel 0, writing 1 to bit 1 removes channel 1 etc.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] channel_mask Channels to be removed from the group.
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* @param[in] channel_group Channel group.
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*/
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__STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
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uint32_t channel_mask,
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nrf_dppi_channel_group_t channel_group);
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/**
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* @brief Function for removing all DPPI channels from a channel group.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] group Channel group.
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*/
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__STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
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nrf_dppi_channel_group_t group);
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/**
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* @brief Function for enabling a channel group.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] group Channel group.
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*/
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__STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,
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nrf_dppi_channel_group_t group);
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/**
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* @brief Function for disabling a channel group.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] group Channel group.
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*/
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__STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
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nrf_dppi_channel_group_t group);
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/**
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* @brief Function for getting the ENABLE task associated with the specified channel group.
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*
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* @param[in] index Channel group index.
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*
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* @return Requested ENABLE task.
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*/
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__STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index);
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/**
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* @brief Function for getting the DISABLE task associated with the specified channel group.
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*
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* @param[in] index Channel group index.
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*
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* @return Requested DISABLE task.
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*/
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__STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index);
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#ifndef SUPPRESS_INLINE_IMPLEMENTATION
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__STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task)
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{
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*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) dppi_task)) = 1;
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}
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__STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
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nrf_dppi_task_t task)
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{
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return (uint32_t) ((uint8_t *) p_reg + (uint32_t ) task);
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}
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__STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel)
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{
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return ((p_reg->CHEN & (DPPIC_CHEN_CH0_Enabled << (DPPIC_CHEN_CH0_Pos + channel))) != 0);
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}
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__STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg)
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{
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p_reg->CHENCLR = 0xFFFFFFFFuL;
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}
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__STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask)
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{
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p_reg->CHENSET = mask;
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}
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__STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask)
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{
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p_reg->CHENCLR = mask;
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}
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__STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
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nrf_dppi_task_t task,
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uint8_t channel)
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{
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*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
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((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
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}
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__STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task)
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{
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*((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
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}
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__STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
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uint32_t channel_mask,
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nrf_dppi_channel_group_t channel_group)
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{
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p_reg->CHG[(uint32_t) channel_group] =
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p_reg->CHG[(uint32_t) channel_group] | (channel_mask);
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}
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__STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
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uint32_t channel_mask,
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nrf_dppi_channel_group_t channel_group)
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{
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p_reg->CHG[(uint32_t) channel_group] =
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p_reg->CHG[(uint32_t) channel_group] & ~(channel_mask);
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}
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__STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
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nrf_dppi_channel_group_t group)
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{
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p_reg->CHG[(uint32_t) group] = 0;
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}
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__STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg, nrf_dppi_channel_group_t group)
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{
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p_reg->TASKS_CHG[(uint32_t) group].EN = 1;
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}
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__STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
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nrf_dppi_channel_group_t group)
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{
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p_reg->TASKS_CHG[(uint32_t) group].DIS = 1;
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}
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__STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index)
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{
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NRFX_ASSERT(index < NRFX_ARRAY_SIZE(NRF_DPPIC->TASKS_CHG));
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return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].EN);
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}
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__STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index)
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{
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NRFX_ASSERT(index < NRFX_ARRAY_SIZE(NRF_DPPIC->TASKS_CHG));
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return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].DIS);
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}
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#endif // SUPPRESS_INLINE_IMPLEMENTATION
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif // NRF_DPPIC_H__
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