INitial commit

controller-board/README.md

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+# OSH Park-compatible 2 Layer KiCad Template
+
+This is a KiCad template to simplify making printed circuit boards.  
+
+It comes with all the design rules to meet the 2-layer OSH Park specs and stackup. 
+
+- <a href="http://docs.oshpark.com/services/two-layer/">OSH Park Two Layer Specs</a>
+- <a href="http://docs.oshpark.com/design-tools/kicad">OSH Park KiCad help</a>
+
+### Instructions
+
+1. Open KiCad.
+1. Open Preferences > Configure Paths and note the value of 'KICAD_PTEMPLATES'.
+1. In KiCad, open File > New Project > New Project from Template.
+1. Select the location of your new project. The name of the folder will be the name of your project.
+1. The templates with folders in the 'KICAD_PTEMPLATES' are listed under 'Portable Templates" tab.
+1. Select the template and click 'OK'.
+1. Your project now exists, so you can open EESchema and PCBNew and design as usual.
+

controller-board/controller-board-cache.lib

@@ -0,0 +1,390 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Connector_Generic_Conn_01x02
+#
+DEF Connector_Generic_Conn_01x02 J 0 40 Y N 1 F N
+F0 "J" 0 100 50 H V C CNN
+F1 "Connector_Generic_Conn_01x02" 0 -200 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_1x??_*
+$ENDFPLIST
+DRAW
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 50 50 -150 1 1 10 f
+X Pin_1 1 -200 0 150 R 50 50 1 1 P
+X Pin_2 2 -200 -100 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Connector_Generic_Conn_01x03
+#
+DEF Connector_Generic_Conn_01x03 J 0 40 Y N 1 F N
+F0 "J" 0 200 50 H V C CNN
+F1 "Connector_Generic_Conn_01x03" 0 -200 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_1x??_*
+$ENDFPLIST
+DRAW
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 105 0 95 1 1 6 N
+S -50 150 50 -150 1 1 10 f
+X Pin_1 1 -200 100 150 R 50 50 1 1 P
+X Pin_2 2 -200 0 150 R 50 50 1 1 P
+X Pin_3 3 -200 -100 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Connector_Generic_Conn_01x04
+#
+DEF Connector_Generic_Conn_01x04 J 0 40 Y N 1 F N
+F0 "J" 0 200 50 H V C CNN
+F1 "Connector_Generic_Conn_01x04" 0 -300 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_1x??_*
+$ENDFPLIST
+DRAW
+S -50 -195 0 -205 1 1 6 N
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 105 0 95 1 1 6 N
+S -50 150 50 -250 1 1 10 f
+X Pin_1 1 -200 100 150 R 50 50 1 1 P
+X Pin_2 2 -200 0 150 R 50 50 1 1 P
+X Pin_3 3 -200 -100 150 R 50 50 1 1 P
+X Pin_4 4 -200 -200 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Connector_Generic_Conn_01x05
+#
+DEF Connector_Generic_Conn_01x05 J 0 40 Y N 1 F N
+F0 "J" 0 300 50 H V C CNN
+F1 "Connector_Generic_Conn_01x05" 0 -300 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_1x??_*
+$ENDFPLIST
+DRAW
+S -50 -195 0 -205 1 1 6 N
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 105 0 95 1 1 6 N
+S -50 205 0 195 1 1 6 N
+S -50 250 50 -250 1 1 10 f
+X Pin_1 1 -200 200 150 R 50 50 1 1 P
+X Pin_2 2 -200 100 150 R 50 50 1 1 P
+X Pin_3 3 -200 0 150 R 50 50 1 1 P
+X Pin_4 4 -200 -100 150 R 50 50 1 1 P
+X Pin_5 5 -200 -200 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Connector_Generic_Conn_02x04_Odd_Even
+#
+DEF Connector_Generic_Conn_02x04_Odd_Even J 0 40 Y N 1 F N
+F0 "J" 50 200 50 H V C CNN
+F1 "Connector_Generic_Conn_02x04_Odd_Even" 50 -300 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_2x??_*
+$ENDFPLIST
+DRAW
+S -50 -195 0 -205 1 1 6 N
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 105 0 95 1 1 6 N
+S -50 150 150 -250 1 1 10 f
+S 150 -195 100 -205 1 1 6 N
+S 150 -95 100 -105 1 1 6 N
+S 150 5 100 -5 1 1 6 N
+S 150 105 100 95 1 1 6 N
+X Pin_1 1 -200 100 150 R 50 50 1 1 P
+X Pin_2 2 300 100 150 L 50 50 1 1 P
+X Pin_3 3 -200 0 150 R 50 50 1 1 P
+X Pin_4 4 300 0 150 L 50 50 1 1 P
+X Pin_5 5 -200 -100 150 R 50 50 1 1 P
+X Pin_6 6 300 -100 150 L 50 50 1 1 P
+X Pin_7 7 -200 -200 150 R 50 50 1 1 P
+X Pin_8 8 300 -200 150 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Connector_USB_B_Micro
+#
+DEF Connector_USB_B_Micro J 0 40 Y Y 1 F N
+F0 "J" -200 450 50 H V L CNN
+F1 "Connector_USB_B_Micro" -200 350 50 H V L CNN
+F2 "" 150 -50 50 H I C CNN
+F3 "" 150 -50 50 H I C CNN
+ALIAS USB_B_Mini
+$FPLIST
+ USB*
+$ENDFPLIST
+DRAW
+C -150 85 25 0 1 10 F
+C -25 135 15 0 1 10 F
+S -200 -300 200 300 0 1 10 f
+S -5 -300 5 -270 0 1 0 N
+S 10 50 -20 20 0 1 10 F
+S 200 -205 170 -195 0 1 0 N
+S 200 -105 170 -95 0 1 0 N
+S 200 -5 170 5 0 1 0 N
+S 200 195 170 205 0 1 0 N
+P 2 0 1 10 -75 85 25 85 N
+P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N
+P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N
+P 4 0 1 10 25 110 25 60 75 85 25 110 F
+P 5 0 1 0 -170 220 -70 220 -80 190 -160 190 -170 220 F
+P 9 0 1 0 -185 230 -185 220 -175 190 -175 180 -65 180 -65 190 -55 220 -55 230 -185 230 N
+X VBUS 1 300 200 100 L 50 50 1 1 w
+X D- 2 300 -100 100 L 50 50 1 1 B
+X D+ 3 300 0 100 L 50 50 1 1 B
+X ID 4 300 -200 100 L 50 50 1 1 P
+X GND 5 0 -400 100 U 50 50 1 1 w
+X Shield 6 -100 -400 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_C_Small
+#
+DEF Device_C_Small C 0 10 N N 1 F N
+F0 "C" 10 70 50 H V L CNN
+F1 "Device_C_Small" 10 -80 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 13 -60 -20 60 -20 N
+P 2 0 1 12 -60 20 60 20 N
+X ~ 1 0 100 80 D 50 50 1 1 P
+X ~ 2 0 -100 80 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_Q_NMOS_GSD
+#
+DEF Device_Q_NMOS_GSD Q 0 0 Y N 1 F N
+F0 "Q" 200 50 50 H V L CNN
+F1 "Device_Q_NMOS_GSD" 200 -50 50 H V L CNN
+F2 "" 200 100 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 65 0 110 0 1 10 N
+C 100 -70 10 0 1 0 F
+C 100 70 10 0 1 0 F
+P 2 0 1 0 10 0 -100 0 N
+P 2 0 1 10 10 75 10 -75 N
+P 2 0 1 10 30 -50 30 -90 N
+P 2 0 1 10 30 20 30 -20 N
+P 2 0 1 10 30 90 30 50 N
+P 2 0 1 0 100 100 100 70 N
+P 3 0 1 0 100 -100 100 0 30 0 N
+P 4 0 1 0 30 -70 130 -70 130 70 30 70 N
+P 4 0 1 0 40 0 80 15 80 -15 40 0 F
+P 4 0 1 0 110 20 115 15 145 15 150 10 N
+P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
+X G 1 -200 0 100 R 50 50 1 1 I
+X S 2 100 -200 100 U 50 50 1 1 P
+X D 3 100 200 100 D 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_R_Small
+#
+DEF Device_R_Small R 0 10 N N 1 F N
+F0 "R" 30 20 50 H V L CNN
+F1 "Device_R_Small" 30 -40 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*
+$ENDFPLIST
+DRAW
+S -30 70 30 -70 0 1 8 N
+X ~ 1 0 100 30 D 50 50 1 1 P
+X ~ 2 0 -100 30 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Driver_Motor_DRV8837C
+#
+DEF Driver_Motor_DRV8837C U 0 20 Y Y 1 F N
+F0 "U" 250 450 50 H V C CNN
+F1 "Driver_Motor_DRV8837C" -400 450 50 H V C CNN
+F2 "Package_SON:WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm" 0 -850 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS DRV8837
+$FPLIST
+ WSON*1EP*2x2mm*P0.5mm*
+$ENDFPLIST
+DRAW
+S -300 400 300 -400 0 1 10 f
+X VM 1 0 500 100 D 50 50 1 1 W
+X OUT1 2 400 300 100 L 50 50 1 1 O
+X OUT2 3 400 -300 100 L 50 50 1 1 O
+X GND 4 0 -500 100 U 50 50 1 1 W
+X IN2 5 -400 -100 100 R 50 50 1 1 I
+X IN1 6 -400 0 100 R 50 50 1 1 I
+X ~SLEEP 7 -400 100 100 R 50 50 1 1 I
+X VCC 8 -100 500 100 D 50 50 1 1 W
+X GND 9 0 -500 100 U 50 50 1 1 P N
+ENDDRAW
+ENDDEF
+#
+# Interface_USB_FT230XS
+#
+DEF Interface_USB_FT230XS U 0 20 Y Y 1 F N
+F0 "U" -550 600 50 H V L CNN
+F1 "Interface_USB_FT230XS" 300 600 50 H V L CNN
+F2 "Package_SO:SSOP-16_3.9x4.9mm_P0.635mm" 1000 -600 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ SSOP*3.9x4.9*P0.635mm*
+$ENDFPLIST
+DRAW
+S -550 550 550 -550 0 1 10 f
+X TXD 1 700 400 150 L 50 50 1 1 O
+X 3V3OUT 10 -700 400 150 R 50 50 1 1 w
+X ~RESET 11 -700 -200 150 R 50 50 1 1 I
+X VCC 12 -100 700 150 D 50 50 1 1 W
+X GND 13 100 -700 150 U 50 50 1 1 W
+X CBUS1 14 700 -200 150 L 50 50 1 1 B
+X CBUS0 15 700 -100 150 L 50 50 1 1 B
+X CBUS3 16 700 -400 150 L 50 50 1 1 B
+X ~RTS 2 700 200 150 L 50 50 1 1 O
+X VCCIO 3 100 700 150 D 50 50 1 1 W
+X RXD 4 700 300 150 L 50 50 1 1 I
+X GND 5 -100 -700 150 U 50 50 1 1 W
+X ~CTS 6 700 100 150 L 50 50 1 1 I
+X CBUS2 7 700 -300 150 L 50 50 1 1 B
+X USBDP 8 -700 0 150 R 50 50 1 1 B
+X USBDM 9 -700 100 150 R 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# Logic_LevelTranslator_NLSV2T244D
+#
+DEF Logic_LevelTranslator_NLSV2T244D U 0 20 Y Y 1 F N
+F0 "U" -250 450 50 H V C CNN
+F1 "Logic_LevelTranslator_NLSV2T244D" 150 450 50 H V L CNN
+F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 50 -550 50 H I C CNN
+F3 "" -900 -550 50 H I C CNN
+$FPLIST
+ SOIC*3.9x4.9mm*P1.27mm*
+$ENDFPLIST
+DRAW
+S -300 400 300 -400 0 1 10 f
+P 2 0 1 0 -150 -100 -50 -100 N
+P 2 0 1 0 -150 100 -50 100 N
+P 2 0 1 0 150 -100 50 -100 N
+P 2 0 1 0 150 100 50 100 N
+P 4 0 1 0 -50 -150 -50 -50 50 -100 -50 -150 N
+P 4 0 1 0 -50 50 -50 150 50 100 -50 50 N
+X VCCA 1 -100 500 100 D 50 50 1 1 W
+X A1 2 -400 100 100 R 50 50 1 1 I
+X A2 3 -400 -100 100 R 50 50 1 1 I
+X ~OE 4 -400 -300 100 R 50 50 1 1 I
+X GND 5 0 -500 100 U 50 50 1 1 W
+X B2 6 400 -100 100 L 50 50 1 1 O
+X B1 7 400 100 100 L 50 50 1 1 O
+X VCCB 8 100 500 100 D 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# MCU_ST_STM32L0_STM32L011F4Px
+#
+DEF MCU_ST_STM32L0_STM32L011F4Px U 0 20 Y Y 1 F N
+F0 "U" -400 650 50 H V L CNN
+F1 "MCU_ST_STM32L0_STM32L011F4Px" 100 650 50 H V L CNN
+F2 "Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm" -400 -700 50 H I R CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS STM32L011F4Px
+$FPLIST
+ TSSOP*4.4x6.5mm*P0.65mm*
+$ENDFPLIST
+DRAW
+S -400 -700 300 600 0 1 10 f
+X PB9 1 -500 -600 100 R 50 50 1 1 B
+X PA4 10 400 100 100 L 50 50 1 1 B
+X PA5 11 400 0 100 L 50 50 1 1 B
+X PA6 12 400 -100 100 L 50 50 1 1 B
+X PA7 13 400 -200 100 L 50 50 1 1 B
+X PB1 14 -500 -500 100 R 50 50 1 1 B
+X VSS 15 -100 -800 100 U 50 50 1 1 W
+X VDD 16 -100 700 100 D 50 50 1 1 W
+X PA9 17 400 -300 100 L 50 50 1 1 B
+X PA10 18 400 -400 100 L 50 50 1 1 B
+X PA13 19 400 -500 100 L 50 50 1 1 B
+X PC14 2 -500 -200 100 R 50 50 1 1 B
+X PA14 20 400 -600 100 L 50 50 1 1 B
+X PC15 3 -500 -300 100 R 50 50 1 1 B
+X NRST 4 -500 500 100 R 50 50 1 1 I
+X VDDA 5 0 700 100 D 50 50 1 1 W
+X PA0 6 400 500 100 L 50 50 1 1 B
+X PA1 7 400 400 100 L 50 50 1 1 B
+X PA2 8 400 300 100 L 50 50 1 1 B
+X PA3 9 400 200 100 L 50 50 1 1 B
+ENDDRAW
+ENDDEF
+#
+# Transistor_FET_BUK9M52-40EX
+#
+DEF Transistor_FET_BUK9M52-40EX Q 0 20 Y N 1 F N
+F0 "Q" 200 75 50 H V L CNN
+F1 "Transistor_FET_BUK9M52-40EX" 200 0 50 H V L CNN
+F2 "Package_TO_SOT_SMD:LFPAK33" 200 -75 50 H I L CIN
+F3 "" 0 0 50 V I L CNN
+ALIAS BUK9M85-60EX BUK7M45-40EX BUK9M52-40EX BUK9M42-60EX BUK9M14-40EX BUK9M24-60EX BUK9M10-30EX BUK9M11-40EX BUK7M10-40EX BUK7M15-60EX BUK7M19-60EX BUK9M9R1-40EX BUK9M6R6-30EX BUK9M12-60EX BUK7M9R9-60EX BUK7M42-60EX BUK9M156-100EX BUK7M33-60EX BUK7M21-40EX BUK9M43-100EX BUK7M12-60EX BUK9M15-60EX BUK7M27-80EX BUK9M19-60EX BUK9M5R2-30EX BUK7M17-80EX BUK9M7R2-40EX BUK9M34-100EX BUK9M23-80EX BUK7M67-60EX BUK9M24-40EX BUK9M120-100EX BUK9M17-30EX BUK7M12-40EX BUK9M28-80EX BUK7M8R0-40EX BUK9M35-80EX BUK7M6R3-40EX BUK7M22-80EX
+$FPLIST
+ LFPAK33*
+$ENDFPLIST
+DRAW
+C 65 0 110 0 1 10 N
+C 100 -70 10 0 1 0 F
+C 100 70 10 0 1 0 F
+P 2 0 1 0 10 0 -100 0 N
+P 2 0 1 10 10 75 10 -75 N
+P 2 0 1 10 30 -50 30 -90 N
+P 2 0 1 10 30 20 30 -20 N
+P 2 0 1 10 30 90 30 50 N
+P 2 0 1 0 100 100 100 70 N
+P 3 0 1 0 100 -100 100 0 30 0 N
+P 4 0 1 0 30 -70 130 -70 130 70 30 70 N
+P 4 0 1 0 40 0 80 15 80 -15 40 0 F
+P 4 0 1 0 110 20 115 15 145 15 150 10 N
+P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
+X S 1 100 -200 100 U 50 50 1 1 P
+X S 2 100 -200 100 U 50 50 1 1 P N
+X S 3 100 -200 100 U 50 50 1 1 P N
+X G 4 -200 0 100 R 50 50 1 1 P
+X D 5 100 200 100 D 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# power_GND
+#
+DEF power_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "power_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+#End Library

controller-board/controller-board.bak

@@ -0,0 +1,17 @@
+EESchema Schematic File Version 2
+LIBS:power
+EELAYER 25 0
+EELAYER END
+$Descr USLetter 11000 8500
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$EndSCHEMATC

controller-board/controller-board.kicad_pcb

@@ -0,0 +1,117 @@
+(kicad_pcb (version 20171130) (host pcbnew 5.0.0)
+
+  (general
+    (thickness 1.6)
+    (drawings 1)
+    (tracks 0)
+    (zones 0)
+    (modules 0)
+    (nets 1)
+  )
+
+  (page USLetter)
+  (title_block
+    (title "Project Title")
+  )
+
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (44 Edge.Cuts user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.1524)
+    (user_trace_width 0.1524)
+    (user_trace_width 0.2)
+    (user_trace_width 0.25)
+    (user_trace_width 0.3)
+    (user_trace_width 0.5)
+    (user_trace_width 0.75)
+    (user_trace_width 1.25)
+    (trace_clearance 0.1524)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.1524)
+    (segment_width 0.1524)
+    (edge_width 0.1524)
+    (via_size 0.6858)
+    (via_drill 0.3302)
+    (via_min_size 0.6858)
+    (via_min_drill 0.3302)
+    (user_via 0.6858 0.3302)
+    (user_via 0.762 0.4064)
+    (user_via 0.8636 0.508)
+    (uvia_size 0.6858)
+    (uvia_drill 0.3302)
+    (uvias_allowed no)
+    (uvia_min_size 0)
+    (uvia_min_drill 0)
+    (pcb_text_width 0.1524)
+    (pcb_text_size 1.016 1.016)
+    (mod_edge_width 0.1524)
+    (mod_text_size 1.016 1.016)
+    (mod_text_width 0.1524)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.0508)
+    (solder_mask_min_width 0.1016)
+    (pad_to_paste_clearance -0.0762)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFEDF7D)
+    (pcbplotparams
+      (layerselection 0x310fc_80000001)
+      (usegerberextensions true)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "gerbers"))
+  )
+
+  (net 0 "")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.1524)
+    (trace_width 0.1524)
+    (via_dia 0.6858)
+    (via_drill 0.3302)
+    (uvia_dia 0.6858)
+    (uvia_drill 0.3302)
+  )
+
+  (gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n5. ROHS COMPLIANCE IS NOT REQUIRED.\n6. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n   SOLDER MASK (ANY COLOR) OVER BARE COPPER. \n7. SILK: BOTH SIDES OF THE BOARD SHALL HAVE \n   WHITE SILKSCREEN. DO NOT PLACE SILK OVER BARE COPPER.\n8. FINISH: HASL/ENIG.\n9. MINIMUM TRACE WIDTH - 0.006 INCH.\n   MINIMUM SPACE - 0.006 INCH.\n   MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 113.4872 93.2688) (layer Dwgs.User)
+    (effects (font (size 2.54 2.54) (thickness 0.254)) (justify left))
+  )
+
+)

controller-board/controller-board.kicad_pcb-bak

@@ -0,0 +1,116 @@
+(kicad_pcb (version 20171130) (host pcbnew 5.0.0)
+
+  (general
+    (thickness 1.6)
+    (drawings 1)
+    (tracks 0)
+    (zones 0)
+    (modules 0)
+    (nets 1)
+  )
+
+  (page USLetter)
+  (title_block
+    (title "Project Title")
+  )
+
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (44 Edge.Cuts user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.1524)
+    (user_trace_width 0.1524)
+    (user_trace_width 0.254)
+    (user_trace_width 0.3302)
+    (user_trace_width 0.508)
+    (user_trace_width 0.762)
+    (user_trace_width 1.27)
+    (trace_clearance 0.1524)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.1524)
+    (segment_width 0.1524)
+    (edge_width 0.1524)
+    (via_size 0.6858)
+    (via_drill 0.3302)
+    (via_min_size 0.6858)
+    (via_min_drill 0.3302)
+    (user_via 0.6858 0.3302)
+    (user_via 0.762 0.4064)
+    (user_via 0.8636 0.508)
+    (uvia_size 0.6858)
+    (uvia_drill 0.3302)
+    (uvias_allowed no)
+    (uvia_min_size 0)
+    (uvia_min_drill 0)
+    (pcb_text_width 0.1524)
+    (pcb_text_size 1.016 1.016)
+    (mod_edge_width 0.1524)
+    (mod_text_size 1.016 1.016)
+    (mod_text_width 0.1524)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.0508)
+    (solder_mask_min_width 0.1016)
+    (pad_to_paste_clearance -0.0762)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFEDF7D)
+    (pcbplotparams
+      (layerselection 0x310fc_80000001)
+      (usegerberextensions true)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "gerbers"))
+  )
+
+  (net 0 "")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.1524)
+    (trace_width 0.1524)
+    (via_dia 0.6858)
+    (via_drill 0.3302)
+    (uvia_dia 0.6858)
+    (uvia_drill 0.3302)
+  )
+
+  (gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n5. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n   SOLDER MASK (ANY COLOR) OVER BARE COPPER. \n6. SILK: BOTH SIDES OF THE BOARD SHALL HAVE \n   WHITE SILKSCREEN. DO NOT PLACE SILK OVER BARE COPPER.\n7. FINISH: HASL/ENIG.\n8. MINIMUM TRACE WIDTH - 0.006 INCH.\n   MINIMUM SPACE - 0.006 INCH.\n   MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 113.4872 93.2688) (layer Dwgs.User)
+    (effects (font (size 2.54 2.54) (thickness 0.254)) (justify left))
+  )
+
+)

controller-board/controller-board.pro

@@ -0,0 +1,41 @@
+update=Tue 11 Oct 2016 05:25:07 PM PDT
+version=1
+last_client=kicad
+[cvpcb]
+version=1
+NetIExt=net
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.016000000000
+PcbTextSizeH=1.016000000000
+PcbTextThickness=0.152400000000
+ModuleTextSizeV=1.016000000000
+ModuleTextSizeH=1.016000000000
+ModuleTextSizeThickness=0.152400000000
+SolderMaskClearance=0.003000000000
+SolderMaskMinWidth=0.004000000000
+DrawSegmentWidth=0.152400000000
+BoardOutlineThickness=0.152400000000
+ModuleOutlineThickness=0.152400000000
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=50
+[general]
+version=1