Reorganize code somewhat to reduce directory depth; USART is working, working on SysTick now
This commit is contained in:
parent
9d29604b47
commit
a70bb3d733
|
@ -1,2 +1,3 @@
|
|||
bin/
|
||||
*.elf
|
||||
*.bin
|
|
@ -1,4 +1,4 @@
|
|||
PROJECT = ztheta-controller
|
||||
PROJECT = controller
|
||||
BUILD_DIR = bin
|
||||
|
||||
#SHARED_DIR =
|
||||
|
@ -6,13 +6,13 @@ CFILES = main.c
|
|||
|
||||
# TODO - you will need to edit these two lines!
|
||||
DEVICE=stm32l011f4p6
|
||||
OOCD_FILE = board/stm32f4discovery.cfg
|
||||
OOCD_FILE = ft232h.cfg
|
||||
|
||||
# You shouldn't have to edit anything below here.
|
||||
VPATH += $(SHARED_DIR)
|
||||
INCLUDES += $(patsubst %,-I%, . $(SHARED_DIR))
|
||||
OPENCM3_DIR=../libopencm3
|
||||
OPENCM3_DIR=libopencm3
|
||||
|
||||
include $(OPENCM3_DIR)/mk/genlink-config.mk
|
||||
include ../rules.mk
|
||||
include rules.mk
|
||||
include $(OPENCM3_DIR)/mk/genlink-rules.mk
|
|
@ -0,0 +1,20 @@
|
|||
adapter driver ftdi
|
||||
transport select swd
|
||||
ftdi_vid_pid 0x0403 0x6014
|
||||
|
||||
ftdi_layout_init 0xfff8 0xfffb
|
||||
|
||||
ftdi_layout_signal SWD_EN -data 0
|
||||
ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
|
||||
ftdi_layout_signal nSRST -data 0x0200 -oe 0x0200
|
||||
|
||||
source [find target/stm32l0.cfg]
|
||||
|
||||
$_TARGETNAME configure -event reset-end {
|
||||
echo "Remapping Flash to address 0x00000000"
|
||||
# RCC_APB2ENR <= 0x1
|
||||
mww 0x40021034 0x1
|
||||
# SYSCFG_CFGR1 <= 0x0
|
||||
mww 0x40010000 0x0
|
||||
}
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
#include <libopencm3/stm32/rcc.h>
|
||||
#include <libopencm3/stm32/gpio.h>
|
||||
#include <libopencm3/stm32/usart.h>
|
||||
|
||||
#include <libopencm3/cm3/systick.h>
|
||||
|
||||
int main(void) {
|
||||
rcc_periph_clock_enable(RCC_GPIOA);
|
||||
rcc_periph_clock_enable(RCC_GPIOB);
|
||||
|
||||
rcc_periph_clock_enable(RCC_USART2);
|
||||
|
||||
// setup PA5-7 and PB1 for the stepper motor gates
|
||||
gpio_clear(GPIOA, GPIO5|GPIO6|GPIO7);
|
||||
gpio_clear(GPIOB, GPIO1);
|
||||
gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO5);
|
||||
gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO6);
|
||||
gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO7);
|
||||
gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO1);
|
||||
|
||||
// setup PA2/3 for USART2_RX and USART2_TX
|
||||
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO2|GPIO3);
|
||||
gpio_set_af(GPIOA, GPIO_AF4, GPIO2|GPIO3);
|
||||
|
||||
// setup USART2 stuff
|
||||
usart_set_baudrate(USART2, 115200);
|
||||
usart_set_databits(USART2, 8);
|
||||
usart_set_stopbits(USART2, USART_STOPBITS_1);
|
||||
usart_set_mode(USART2, USART_MODE_TX_RX);
|
||||
usart_set_parity(USART2, USART_PARITY_NONE);
|
||||
usart_set_flow_control(USART2, USART_FLOWCONTROL_NONE);
|
||||
usart_enable(USART2);
|
||||
|
||||
#if 0
|
||||
// if I need more speed than the internal 2 MHz
|
||||
// setup PA0 as a clock input
|
||||
rcc_bypass_enable(RCC_HSE);
|
||||
rcc_osc_on(RCC_HSE);
|
||||
|
||||
rcc_wait_for_osc_ready(RCC_HSE);
|
||||
rcc_set_sysclk_source(RCC_HSE);
|
||||
#endif
|
||||
|
||||
// setup systick interrupt
|
||||
systick_interrupt_disable();
|
||||
systick_counter_disable();
|
||||
|
||||
systick_set_clocksource(STK_CSR_CLKSOURCE_AHB);
|
||||
systick_set_reload(rcc_ahb_frequency/100000-1);
|
||||
systick_clear();
|
||||
|
||||
systick_interrupt_enable();
|
||||
systick_counter_enable();
|
||||
|
||||
while (1) {
|
||||
if ((USART_ISR(USART2) & USART_ISR_RXNE) != 0) {
|
||||
// TODO process byte
|
||||
uint8_t rx = usart_recv(USART2);
|
||||
usart_send_blocking(USART2, rx);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void SysTick_Handler(void);
|
||||
void SysTick_Handler(void) {
|
||||
}
|
|
@ -1,3 +0,0 @@
|
|||
int main(void) {
|
||||
// TODO
|
||||
}
|
Binary file not shown.
Loading…
Reference in New Issue