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"netclass": "Default", "pattern": "Net-(U21-IIN)" }, { "netclass": "Default", "pattern": "Net-(U16-COMP)" }, { "netclass": "Default", "pattern": "/FPGA/b_home-" }, { "netclass": "Default", "pattern": "Net-(C57-Pad1)" }, { "netclass": "Default", "pattern": "/FPGA/breakout/fltd" }, { "netclass": "Default", "pattern": "/FPGA/breakout/spindle_fwd" }, { "netclass": "Default", "pattern": "/FPGA/a_home-" }, { "netclass": "Default", "pattern": "/FPGA/breakout/b_home+" }, { "netclass": "Default", "pattern": "/FPGA/breakout/spindle_fwd_oc" }, { "netclass": "Default", "pattern": "/CM4_GPIO ( Ethernet, GPIO, SDCARD)/SD_CLK" }, { "netclass": "Default", "pattern": "Net-(C62-Pad1)" }, { "netclass": "Default", "pattern": "/CM4_HighSpeed/PCIE_RX_P" }, { "netclass": "Default", "pattern": "/CM4_HighSpeed/HDMI0_HOTPLUG" }, { "netclass": "Default", "pattern": "Net-(D3-A)" }, { "netclass": "Default", "pattern": "/FPGA/probe" }, { "netclass": "Default", "pattern": "Net-(Q4-B)" }, { "netclass": "Default", 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