83 lines
1.4 KiB
Verilog
83 lines
1.4 KiB
Verilog
module uart_tx_115200(
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input clk_25mhz,
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input rstn,
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output reg tx,
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input [7:0] tx_buf,
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input vld,
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output rdy,
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);
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reg [2:0] b = 0;
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reg [2:0] b_next;
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reg [7:0] counter = 0;
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reg [7:0] counter_next;
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localparam IDLE = 0, START = 1, TX = 2, STOP = 3;
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reg [1:0] state = IDLE;
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reg [1:0] state_next;
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assign rdy = (state == IDLE);
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always @* begin
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case (state)
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IDLE: tx = 1;
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START: tx = 0;
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TX: tx = tx_buf[b];
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STOP: tx = 1;
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endcase
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end
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always @* begin
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state_next = state;
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counter_next = counter;
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b_next = b;
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if (rstn) begin
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if (counter == 216) begin
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counter_next = 0;
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b_next = b + 1;
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end else begin
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counter_next = counter + 1;
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end
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case (state)
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IDLE: begin
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if (vld) begin
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state_next = START;
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counter_next = 0;
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end
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end
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START: begin
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if (counter == 216) begin
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state_next = TX;
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b_next = 0;
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end
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end
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TX: begin
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if ((counter == 216) && (b == 7)) begin
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state_next = STOP;
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end
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end
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STOP: begin
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if (counter == 216) begin
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state_next = IDLE;
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end
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end
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endcase
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end else begin
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state_next = IDLE;
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counter_next = 0;
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b_next = 0;
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end
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end
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always @(posedge clk_25mhz) begin
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state <= state_next;
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counter <= counter_next;
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b <= b_next;
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end
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endmodule
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