bldc-parts.pretty
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Generate some footprints
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2019-12-01 00:21:06 -05:00 |
21-0140.PDF
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Generate some footprints
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2019-12-01 00:21:06 -05:00 |
90-0023.PDF
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Generate some footprints
|
2019-12-01 00:21:06 -05:00 |
AN1914.pdf
|
Save before autofill
|
2019-11-21 06:40:15 -05:00 |
MAX11135-MAX11143-220131.pdf
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Generate library parts for FPGA; I think I'm going to go with the UP5K for the initial prototype and swap out for the LP384 if the LUT usage is low enough
|
2019-11-14 23:41:59 -05:00 |
README.md
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Add README
|
2019-11-12 22:07:31 -05:00 |
autofill_schem.py
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Fix autofill so that autofilling actually works
|
2019-11-22 08:44:22 -05:00 |
bldc-controller-cache.lib
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Autofill/fix footprints, and add footprints for MOSFETs
|
2019-11-29 10:14:19 -05:00 |
bldc-controller.bak
|
Start work in BLDC driver; add DRV8353xx driver
|
2019-11-12 22:06:05 -05:00 |
bldc-controller.kicad_pcb
|
Start work in BLDC driver; add DRV8353xx driver
|
2019-11-12 22:06:05 -05:00 |
bldc-controller.kicad_pcb-bak
|
Start work in BLDC driver; add DRV8353xx driver
|
2019-11-12 22:06:05 -05:00 |
bldc-controller.pro
|
Start work in BLDC driver; add DRV8353xx driver
|
2019-11-12 22:06:05 -05:00 |
bldc-controller.sch
|
Generate some footprints
|
2019-12-01 00:21:06 -05:00 |
bldc-controller.sch-bak
|
Generate some footprints
|
2019-12-01 00:21:06 -05:00 |
drv835x.dcm
|
Start work in BLDC driver; add DRV8353xx driver
|
2019-11-12 22:06:05 -05:00 |
drv835x.lib
|
Finish schematic; TODO source passivess, create all the footpritns
|
2019-11-18 00:32:15 -05:00 |
drv8353.pdf
|
Start work in BLDC driver; add DRV8353xx driver
|
2019-11-12 22:06:05 -05:00 |
esd.dcm
|
Finish schematic; TODO source passivess, create all the footpritns
|
2019-11-18 00:32:15 -05:00 |
esd.lib
|
Finish schematic; TODO source passivess, create all the footpritns
|
2019-11-18 00:32:15 -05:00 |
fp-info-cache
|
Generate some footprints
|
2019-12-01 00:21:06 -05:00 |
fp-lib-table
|
Autofill/fix footprints, and add footprints for MOSFETs
|
2019-11-29 10:14:19 -05:00 |
gen_ice40hx1k_lib.py
|
Generate library parts for FPGA; I think I'm going to go with the UP5K for the initial prototype and swap out for the LP384 if the LUT usage is low enough
|
2019-11-14 23:41:59 -05:00 |
gen_ice40lp1k_cb81_lib.py
|
Generate library parts for FPGA; I think I'm going to go with the UP5K for the initial prototype and swap out for the LP384 if the LUT usage is low enough
|
2019-11-14 23:41:59 -05:00 |
gen_ice40up5k_sg48_lib.py
|
Generate library parts for FPGA; I think I'm going to go with the UP5K for the initial prototype and swap out for the LP384 if the LUT usage is low enough
|
2019-11-14 23:41:59 -05:00 |
gen_maxim_tqfn28.py
|
Generate some footprints
|
2019-12-01 00:21:06 -05:00 |
gen_ti_rgz48.py
|
Generate some footprints
|
2019-12-01 00:21:06 -05:00 |
ice40hx1k_pinout.csv
|
Generate library parts for FPGA; I think I'm going to go with the UP5K for the initial prototype and swap out for the LP384 if the LUT usage is low enough
|
2019-11-14 23:41:59 -05:00 |
ice40hx1k_vq100.dcm
|
Generate library parts for FPGA; I think I'm going to go with the UP5K for the initial prototype and swap out for the LP384 if the LUT usage is low enough
|
2019-11-14 23:41:59 -05:00 |
ice40hx1k_vq100.lib
|
Generate library parts for FPGA; I think I'm going to go with the UP5K for the initial prototype and swap out for the LP384 if the LUT usage is low enough
|
2019-11-14 23:41:59 -05:00 |
ice40lp1k_cb81.dcm
|
Generate library parts for FPGA; I think I'm going to go with the UP5K for the initial prototype and swap out for the LP384 if the LUT usage is low enough
|
2019-11-14 23:41:59 -05:00 |
ice40lp1k_cb81.lib
|
Generate library parts for FPGA; I think I'm going to go with the UP5K for the initial prototype and swap out for the LP384 if the LUT usage is low enough
|
2019-11-14 23:41:59 -05:00 |
ice40lp1k_pinout.csv
|
Generate library parts for FPGA; I think I'm going to go with the UP5K for the initial prototype and swap out for the LP384 if the LUT usage is low enough
|
2019-11-14 23:41:59 -05:00 |
ice40up5k_pinout.csv
|
Generate library parts for FPGA; I think I'm going to go with the UP5K for the initial prototype and swap out for the LP384 if the LUT usage is low enough
|
2019-11-14 23:41:59 -05:00 |
ice40up5k_sg48.dcm
|
Finish schematic; TODO source passivess, create all the footpritns
|
2019-11-18 00:32:15 -05:00 |
ice40up5k_sg48.lib
|
Finish schematic; TODO source passivess, create all the footpritns
|
2019-11-18 00:32:15 -05:00 |
ldos.dcm
|
Finish schematic; TODO source passivess, create all the footpritns
|
2019-11-18 00:32:15 -05:00 |
ldos.lib
|
Finish schematic; TODO source passivess, create all the footpritns
|
2019-11-18 00:32:15 -05:00 |
max11135-max11142.dcm
|
Generate library parts for FPGA; I think I'm going to go with the UP5K for the initial prototype and swap out for the LP384 if the LUT usage is low enough
|
2019-11-14 23:41:59 -05:00 |
max11135-max11142.lib
|
Fix mistake in MAX ADC parts, wire up FPGA TODO all FPGA support parts
|
2019-11-15 07:21:11 -05:00 |
mosfets.dcm
|
Autofill/fix footprints, and add footprints for MOSFETs
|
2019-11-29 10:14:19 -05:00 |
mosfets.lib
|
Autofill/fix footprints, and add footprints for MOSFETs
|
2019-11-29 10:14:19 -05:00 |
sym-lib-table
|
Autofill/fix footprints, and add footprints for MOSFETs
|
2019-11-29 10:14:19 -05:00 |
tlv62566.bck
|
Finish schematic; TODO source passivess, create all the footpritns
|
2019-11-18 00:32:15 -05:00 |
tlv62566.dcm
|
Finish schematic; TODO source passivess, create all the footpritns
|
2019-11-18 00:32:15 -05:00 |
tlv62566.lib
|
Finish schematic; TODO source passivess, create all the footpritns
|
2019-11-18 00:32:15 -05:00 |