83 lines
1.4 KiB
Verilog
83 lines
1.4 KiB
Verilog
module uart_tx_115200(
|
|
input clk_25mhz,
|
|
input rstn,
|
|
output reg tx,
|
|
input [7:0] tx_buf,
|
|
input tx_vld,
|
|
output tx_ack,
|
|
);
|
|
|
|
reg [2:0] bit = 0;
|
|
reg [2:0] bit_next;
|
|
|
|
reg [7:0] counter = 0;
|
|
reg [7:0] counter_next;
|
|
|
|
localparam IDLE = 0, START = 1, TX = 2, STOP = 3;
|
|
|
|
reg [1:0] state = IDLE;
|
|
reg [1:0] state_next;
|
|
|
|
assign tx_ack = (state == IDLE);
|
|
|
|
always @* begin
|
|
case (state)
|
|
IDLE: tx = 1;
|
|
START: tx = 0;
|
|
TX: tx = tx_buf[bit];
|
|
STOP: tx = 1;
|
|
endcase
|
|
end
|
|
|
|
always @* begin
|
|
state_next = state;
|
|
counter_next = counter;
|
|
bit_next = bit;
|
|
|
|
if (rstn) begin
|
|
if (counter == 216) begin
|
|
counter_next = 0;
|
|
bit_next = bit + 1;
|
|
end else begin
|
|
counter_next = counter + 1;
|
|
end
|
|
|
|
case (state)
|
|
IDLE: begin
|
|
if (tx_vld) begin
|
|
state_next = START;
|
|
counter_next = 0;
|
|
end
|
|
end
|
|
START: begin
|
|
if (counter == 216) begin
|
|
state_next = TX;
|
|
bit_next = 0;
|
|
end
|
|
end
|
|
TX: begin
|
|
if ((counter == 216) && (bit == 7)) begin
|
|
state_next = STOP;
|
|
end
|
|
end
|
|
STOP: begin
|
|
if (counter == 216) begin
|
|
state_next = IDLE;
|
|
end
|
|
end
|
|
endcase
|
|
end else begin
|
|
state_next = IDLE;
|
|
counter_next = 0;
|
|
bit_next = 0;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk_25mhz) begin
|
|
state <= state_next;
|
|
counter <= counter_next;
|
|
bit <= bit_next;
|
|
end
|
|
|
|
endmodule
|