34 lines
495 B
Verilog
34 lines
495 B
Verilog
module bldc (
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input clk,
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output dbg_tx,
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output if_int
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);
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reg [7:0] dbg_buf = 8'hac;
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reg dbg_buf_vld = 1;
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wire dbg_tx_ack;
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uart_tx_115200 dbg(
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.clk_25mhz(clk),
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.rstn(1'b1),
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.tx(dbg_tx),
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.tx_buf(dbg_buf),
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.tx_vld(dbg_buf_vld),
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.tx_ack(dbg_tx_ack)
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);
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reg [3:0] tmp = 0;
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assign if_int = tmp[3];
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always @(posedge clk) begin
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tmp <= tmp + 1;
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if (dbg_tx_ack) begin
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dbg_buf <= dbg_buf + 1;
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dbg_buf_vld = 1;
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end else begin
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dbg_buf_vld = 0;
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end
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end
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endmodule
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