144 lines
2.2 KiB
Verilog
144 lines
2.2 KiB
Verilog
`timescale 10ns/10ns
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module top();
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reg clk = 0;
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reg rstn = 1;
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reg adc_so = 1;
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wire adc_si;
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wire adc_sck;
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wire adc_ss;
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reg sck_old = 1;
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reg ss_old = 1;
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wire [1:0] channel;
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wire [11:0] adc_val;
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wire vld;
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reg ack = 0;
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adc_driver dut(
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.clk(clk),
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.rstn(rstn),
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.adc_so(adc_so),
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.adc_si(adc_si),
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.adc_ss(adc_ss),
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.adc_sck(adc_sck),
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.channel(channel),
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.adc_val(adc_val),
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.vld(vld),
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.ack(ack)
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);
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reg configured;
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reg [15:0] out;
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initial begin
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clk = 0;
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rstn = 1;
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adc_so = 1;
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sck_old = 1;
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configured = 0;
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out = 0;
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$dumpfile("adc_driver_tb.vcd");
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$dumpvars;
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end
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always
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#2 clk = !clk;
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reg enabled;
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integer bit_pos;
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integer channel_num;
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integer tosend;
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integer configdata;
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integer adc_pos;
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integer adc_out[3:0];
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integer i;
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initial begin
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bit_pos = 0;
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channel_num = 0;
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tosend = 0;
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enabled = 0;
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configdata = 0;
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adc_pos = 0;
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adc_so = 1;
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for (i = 0; i < 4; i++)
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adc_out[i] = 0;
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end
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always @* begin
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case (adc_pos[1:0])
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2'b00: out = 16'h01ff;
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2'b01: out = 16'h1fff;
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2'b10: out = 16'h2dea;
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2'b11: out = 16'h3caf;
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endcase
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end
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always @(posedge clk) begin
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if (~adc_ss & ss_old) begin
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enabled <= 1;
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bit_pos <= 0;
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end
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if (enabled) begin
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if (!configured) begin
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// load into configdata if it hasn't
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// been configured yet
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if (~sck_old & adc_sck) begin
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configdata <= (configdata << 1) | adc_si;
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if (bit_pos >= 15) begin
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configured <= 1;
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bit_pos <= 0;
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end else
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bit_pos <= bit_pos + 1;
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end
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end else begin
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if (~sck_old & adc_sck) begin
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// TODO make sure the input is zero
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end
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if (sck_old & ~adc_sck) begin
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// otherwise start loading in adc data
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if (bit_pos >= 15) begin
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bit_pos <= 0;
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end else
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bit_pos <= bit_pos + 1;
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adc_so <= out[15-bit_pos];
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end
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end
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end
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if (vld & configured & ~ack) begin
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adc_pos <= adc_pos + 1;
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adc_out[channel] <= adc_val;
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ack <= 1;
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if (channel == 3) begin
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// TODO check configdata
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// TODO check adc values
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$finish;
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end
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end else
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ack <= 0;
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ss_old <= adc_ss;
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sck_old <= adc_sck;
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end
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initial begin
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#50000
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$finish;
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end
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endmodule
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