164 lines
3.5 KiB
Verilog
164 lines
3.5 KiB
Verilog
module adc_driver(
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input clk,
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input rstn,
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input adc_so,
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output adc_si,
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output adc_ss,
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output adc_sck,
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output [1:0] channel,
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output [11:0] adc_val,
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output reg vld,
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input ack
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);
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reg [1:0] channel_ff = 0;
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reg [11:0] adc_val_ff = 0;
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reg vld_ff = 0;
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assign channel = channel_ff;
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assign adc_val = adc_val_ff;
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assign vld = vld_ff;
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reg [2:0] sck_strobe = 0;
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wire strobe = &sck_strobe;
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always @(posedge clk) begin
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if (rstn)
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sck_strobe <= sck_strobe + 1;
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else
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sck_strobe <= 0;
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end
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localparam INIT = 0, CONFIG = 1, ADC = 2;
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reg [1:0] state = INIT;
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reg [1:0] state_next;
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reg [3:0] bit_pos = 0;
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reg [3:0] bit_pos_next;
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reg [15:0] so_ff = 0;
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reg [15:0] so_ff_next;
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reg write_out;
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reg sck_next;
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reg ss_next;
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reg si_next;
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reg adc_si_ff = 1;
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reg adc_ss_ff = 1;
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reg adc_sck_ff = 1;
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assign adc_si = adc_si_ff;
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assign adc_ss = adc_ss_ff;
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assign adc_sck = adc_sck_ff;
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wire [15:0] config_word;
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wire config_bit;
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assign config_word = {
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1'b0, // ADC Mode Control
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4'b0100, // Standard_Ext
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4'b0011, // Up to AIN3
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2'b01, // reset FIFO
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2'b00, // normal PM mode
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1'b1, // include channel number in output
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1'b0, // SWCNV enable, not used in external clock mode
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1'b0 // reserved
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};
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assign config_bit = config_word[15-bit_pos];
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always @* begin
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state_next = state;
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bit_pos_next = bit_pos;
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write_out = 0;
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so_ff_next = so_ff;
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sck_next = 1;
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ss_next = 1;
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if (rstn) begin
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// latch sck and ss state until the strobe happens
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si_next = adc_si;
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ss_next = adc_ss;
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sck_next = adc_sck;
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if (strobe) begin
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case (state)
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INIT: begin
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ss_next = 0;
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state_next = CONFIG;
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bit_pos_next = 0;
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end
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CONFIG: begin
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ss_next = 0;
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sck_next = ~adc_sck;
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// update on the falling edge
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if (adc_sck) begin
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bit_pos_next = bit_pos + 1;
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si_next = config_bit;
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// deassert slave select so it can be triggered on the next frame
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if (bit_pos == 15) begin
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ss_next = 1;
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//bit_pos_next = 0; // don't need this because it's going to
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// overflow
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end
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end
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// switch state on the rising edge after the overflow
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// and reassert ss to start the next frame
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if (~adc_sck & (bit_pos == 0)) begin
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ss_next = 0;
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state_next = ADC;
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end
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end
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ADC: begin
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ss_next = 0;
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si_next = 0;
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sck_next = ~adc_sck;
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// update bit pos state on the rising edge
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// shift in data as well
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if (~adc_sck) begin
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bit_pos_next = bit_pos + 1;
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so_ff_next = {so_ff[14:0], adc_so};
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// after reading the last bit
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// deassert ss so it can be reasserted on the next rising edge
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if (bit_pos == 15) begin
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ss_next = 1;
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write_out = 1;
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end
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end
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end
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endcase
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end
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end else begin
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state_next = INIT;
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bit_pos_next = 0;
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sck_next = 1;
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ss_next = 1;
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end
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end
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always @(posedge clk) begin
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state <= state_next;
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bit_pos <= bit_pos_next;
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adc_sck_ff <= sck_next;
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adc_ss_ff <= ss_next;
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adc_si_ff <= si_next;
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so_ff <= so_ff_next;
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// write the data out when write_out is asserted
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if (write_out) begin
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{channel_ff, adc_val_ff} <= so_ff_next[13:0];
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vld_ff <= 1;
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end
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// deassert vld when the data is acknowledged
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if (ack)
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vld_ff <= 0;
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end
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endmodule
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