module bram512x8(
input clk,
input [8:0] raddr,
output [7:0] reg rdat,
input [8:0] waddr,
input [7:0] wdat,
input wen
);
reg [7:0] mem[511:0];
always @(posedge clk) begin
if (wen)
mem[waddr] <= wdat;
rdat <= mem[rdat];
end
endmodule