commit cecb4d2270dc2a9415eba0f9c2b3d03bae5d546f
Author: Kelvin Ly <kelvin.ly1618@gmail.com>
Date:   Tue Nov 12 22:06:05 2019 -0500

    Start work in BLDC driver; add DRV8353xx driver

diff --git a/README.md b/README.md
new file mode 100644
index 0000000..6131733
--- /dev/null
+++ b/README.md
@@ -0,0 +1,19 @@
+# OSH Park-compatible 2 Layer KiCad Template
+
+This is a KiCad template to simplify making printed circuit boards.  
+
+It comes with all the design rules to meet the 2-layer OSH Park specs and stackup. 
+
+- <a href="http://docs.oshpark.com/services/two-layer/">OSH Park Two Layer Specs</a>
+- <a href="http://docs.oshpark.com/design-tools/kicad">OSH Park KiCad help</a>
+
+### Instructions
+
+1. Open KiCad.
+1. Open Preferences > Configure Paths and note the value of 'KICAD_PTEMPLATES'.
+1. In KiCad, open File > New Project > New Project from Template.
+1. Select the location of your new project. The name of the folder will be the name of your project.
+1. The templates with folders in the 'KICAD_PTEMPLATES' are listed under 'Portable Templates" tab.
+1. Select the template and click 'OK'.
+1. Your project now exists, so you can open EESchema and PCBNew and design as usual.
+
diff --git a/bldc-controller-cache.lib b/bldc-controller-cache.lib
new file mode 100644
index 0000000..d4531a4
--- /dev/null
+++ b/bldc-controller-cache.lib
@@ -0,0 +1,155 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# Connector_Generic_Conn_01x02
+#
+DEF Connector_Generic_Conn_01x02 J 0 40 Y N 1 F N
+F0 "J" 0 100 50 H V C CNN
+F1 "Connector_Generic_Conn_01x02" 0 -200 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ Connector*:*_1x??_*
+$ENDFPLIST
+DRAW
+S -50 -95 0 -105 1 1 6 N
+S -50 5 0 -5 1 1 6 N
+S -50 50 50 -150 1 1 10 f
+X Pin_1 1 -200 0 150 R 50 50 1 1 P
+X Pin_2 2 -200 -100 150 R 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_C_Small
+#
+DEF Device_C_Small C 0 10 N N 1 F N
+F0 "C" 10 70 50 H V L CNN
+F1 "Device_C_Small" 10 -80 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 13 -60 -20 60 -20 N
+P 2 0 1 12 -60 20 60 20 N
+X ~ 1 0 100 80 D 50 50 1 1 P
+X ~ 2 0 -100 80 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_Q_NMOS_DGS
+#
+DEF Device_Q_NMOS_DGS Q 0 0 Y N 1 F N
+F0 "Q" 200 50 50 H V L CNN
+F1 "Device_Q_NMOS_DGS" 200 -50 50 H V L CNN
+F2 "" 200 100 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 65 0 111 0 1 10 N
+C 100 -70 11 0 1 0 F
+C 100 70 11 0 1 0 F
+P 2 0 1 0 2 0 10 0 N
+P 2 0 1 0 30 -70 100 -70 N
+P 2 0 1 10 30 -50 30 -90 N
+P 2 0 1 0 30 0 100 0 N
+P 2 0 1 10 30 20 30 -20 N
+P 2 0 1 0 30 70 100 70 N
+P 2 0 1 10 30 90 30 50 N
+P 2 0 1 0 100 -70 100 -100 N
+P 2 0 1 0 100 -70 100 0 N
+P 2 0 1 0 100 100 100 70 N
+P 3 0 1 10 10 75 10 -75 10 -75 N
+P 4 0 1 0 40 0 80 15 80 -15 40 0 F
+P 4 0 1 0 100 -70 130 -70 130 70 100 70 N
+P 4 0 1 0 110 20 115 15 145 15 150 10 N
+P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
+X D 1 100 200 100 D 50 50 1 1 P
+X G 2 -200 0 200 R 50 50 1 1 I
+X S 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_R_Shunt
+#
+DEF Device_R_Shunt R 0 0 N Y 1 F N
+F0 "R" -175 0 50 V V C CNN
+F1 "Device_R_Shunt" -100 0 50 V V C CNN
+F2 "" -70 0 50 V I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ R_*Shunt*
+$ENDFPLIST
+DRAW
+S -40 -100 40 100 0 1 10 N
+P 2 0 1 0 0 -100 50 -100 N
+P 2 0 1 0 50 100 0 100 N
+X 1 1 0 200 100 D 50 50 1 1 P
+X 2 2 150 100 100 L 50 50 1 1 P
+X 3 3 150 -100 100 L 50 50 1 1 P
+X 4 4 0 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# drv835x_DRV8353RSRGZ
+#
+DEF drv835x_DRV8353RSRGZ U 0 20 Y Y 1 F N
+F0 "U" -400 -1350 50 H V L CNN
+F1 "drv835x_DRV8353RSRGZ" 400 1350 50 H V R CNN
+F2 "" 0 0 50 H I L CNN
+F3 "" 0 0 50 H I L CNN
+DRAW
+S -400 1300 400 -1300 0 0 10 f
+X EP 0 0 -1400 100 U 50 50 1 1 P
+X GND 1 -600 1200 200 R 50 50 1 1 P
+X GLA 10 -600 300 200 R 50 50 1 1 O
+X SPA 11 -600 200 200 R 50 50 1 1 I
+X SNA 12 -600 100 200 R 50 50 1 1 I
+X SNB 13 -600 0 200 R 50 50 1 1 I
+X SPB 14 -600 -100 200 R 50 50 1 1 I
+X GLB 15 -600 -200 200 R 50 50 1 1 O
+X SHB 16 -600 -300 200 R 50 50 1 1 I
+X GHB 17 -600 -400 200 R 50 50 1 1 O
+X GHC 18 -600 -500 200 R 50 50 1 1 O
+X SHC 19 -600 -600 200 R 50 50 1 1 I
+X VGLS 2 -600 1100 200 R 50 50 1 1 w
+X GLC 20 -600 -700 200 R 50 50 1 1 O
+X SPC 21 -600 -800 200 R 50 50 1 1 I
+X SNC 22 -600 -900 200 R 50 50 1 1 I
+X SOC 23 -600 -1000 200 R 50 50 1 1 O
+X SOB 24 -600 -1100 200 R 50 50 1 1 O
+X SOA 25 600 -1100 200 L 50 50 1 1 O
+X VREF 26 600 -1000 200 L 50 50 1 1 W
+X AGND 27 600 -900 200 L 50 50 1 1 P
+X nFAULT 28 600 -800 200 L 50 50 1 1 C
+X SDO 29 600 -700 200 L 50 50 1 1 C
+X CPL 3 -600 1000 200 R 50 50 1 1 w
+X SDI 30 600 -600 200 L 50 50 1 1 I
+X SCLK 31 600 -500 200 L 50 50 1 1 I
+X nSCS 32 600 -400 200 L 50 50 1 1 I
+X ENABLE 33 600 -300 200 L 50 50 1 1 I
+X INHA 34 600 -200 200 L 50 50 1 1 I
+X INLA 35 600 -100 200 L 50 50 1 1 I
+X INHB 36 600 0 200 L 50 50 1 1 I
+X INLB 37 600 100 200 L 50 50 1 1 I
+X INHC 38 600 200 200 L 50 50 1 1 I
+X INLC 39 600 300 200 L 50 50 1 1 I
+X CPH 4 -600 900 200 R 50 50 1 1 w
+X DVDD 40 600 400 200 L 50 50 1 1 W
+X DGND 41 600 500 200 L 50 50 1 1 P
+X SW 42 600 600 200 L 50 50 1 1 O
+X VIN 43 600 700 200 L 50 50 1 1 W
+X VCC 44 600 800 200 L 50 50 1 1 W
+X BST 45 600 900 200 L 50 50 1 1 I
+X RCL 46 600 1000 200 L 50 50 1 1 I
+X RT/SD 47 600 1100 200 L 50 50 1 1 I
+X FB 48 600 1200 200 L 50 50 1 1 I
+X VM 5 -600 800 200 R 50 50 1 1 W
+X VDRAIN 6 -600 700 200 R 50 50 1 1 I
+X VCP 7 -600 600 200 R 50 50 1 1 w
+X GHA 8 -600 500 200 R 50 50 1 1 O
+X SHA 9 -600 400 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/bldc-controller.bak b/bldc-controller.bak
new file mode 100644
index 0000000..f2476bf
--- /dev/null
+++ b/bldc-controller.bak
@@ -0,0 +1,17 @@
+EESchema Schematic File Version 2
+LIBS:power
+EELAYER 25 0
+EELAYER END
+$Descr USLetter 11000 8500
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$EndSCHEMATC
diff --git a/bldc-controller.kicad_pcb b/bldc-controller.kicad_pcb
new file mode 100644
index 0000000..d1ed45b
--- /dev/null
+++ b/bldc-controller.kicad_pcb
@@ -0,0 +1,116 @@
+(kicad_pcb (version 20171130) (host pcbnew 5.0.0)
+
+  (general
+    (thickness 1.6)
+    (drawings 1)
+    (tracks 0)
+    (zones 0)
+    (modules 0)
+    (nets 1)
+  )
+
+  (page USLetter)
+  (title_block
+    (title "Project Title")
+  )
+
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (44 Edge.Cuts user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.1524)
+    (user_trace_width 0.1524)
+    (user_trace_width 0.254)
+    (user_trace_width 0.3302)
+    (user_trace_width 0.508)
+    (user_trace_width 0.762)
+    (user_trace_width 1.27)
+    (trace_clearance 0.1524)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.1524)
+    (segment_width 0.1524)
+    (edge_width 0.1524)
+    (via_size 0.6858)
+    (via_drill 0.3302)
+    (via_min_size 0.6858)
+    (via_min_drill 0.3302)
+    (user_via 0.6858 0.3302)
+    (user_via 0.762 0.4064)
+    (user_via 0.8636 0.508)
+    (uvia_size 0.6858)
+    (uvia_drill 0.3302)
+    (uvias_allowed no)
+    (uvia_min_size 0)
+    (uvia_min_drill 0)
+    (pcb_text_width 0.1524)
+    (pcb_text_size 1.016 1.016)
+    (mod_edge_width 0.1524)
+    (mod_text_size 1.016 1.016)
+    (mod_text_width 0.1524)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.0508)
+    (solder_mask_min_width 0.1016)
+    (pad_to_paste_clearance -0.0762)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFEDF7D)
+    (pcbplotparams
+      (layerselection 0x310fc_80000001)
+      (usegerberextensions true)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "gerbers"))
+  )
+
+  (net 0 "")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.1524)
+    (trace_width 0.1524)
+    (via_dia 0.6858)
+    (via_drill 0.3302)
+    (uvia_dia 0.6858)
+    (uvia_drill 0.3302)
+  )
+
+  (gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n5. ROHS COMPLIANCE IS NOT REQUIRED.\n6. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n   SOLDER MASK (ANY COLOR) OVER BARE COPPER. \n7. SILK: BOTH SIDES OF THE BOARD SHALL HAVE \n   WHITE SILKSCREEN. DO NOT PLACE SILK OVER BARE COPPER.\n8. FINISH: HASL/ENIG.\n9. MINIMUM TRACE WIDTH - 0.006 INCH.\n   MINIMUM SPACE - 0.006 INCH.\n   MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 113.4872 93.2688) (layer Dwgs.User)
+    (effects (font (size 2.54 2.54) (thickness 0.254)) (justify left))
+  )
+
+)
diff --git a/bldc-controller.kicad_pcb-bak b/bldc-controller.kicad_pcb-bak
new file mode 100644
index 0000000..79b3eab
--- /dev/null
+++ b/bldc-controller.kicad_pcb-bak
@@ -0,0 +1,116 @@
+(kicad_pcb (version 20171130) (host pcbnew 5.0.0)
+
+  (general
+    (thickness 1.6)
+    (drawings 1)
+    (tracks 0)
+    (zones 0)
+    (modules 0)
+    (nets 1)
+  )
+
+  (page USLetter)
+  (title_block
+    (title "Project Title")
+  )
+
+  (layers
+    (0 F.Cu signal)
+    (31 B.Cu signal)
+    (34 B.Paste user)
+    (35 F.Paste user)
+    (36 B.SilkS user)
+    (37 F.SilkS user)
+    (38 B.Mask user)
+    (39 F.Mask user)
+    (40 Dwgs.User user)
+    (44 Edge.Cuts user)
+    (46 B.CrtYd user)
+    (47 F.CrtYd user)
+    (48 B.Fab user)
+    (49 F.Fab user)
+  )
+
+  (setup
+    (last_trace_width 0.1524)
+    (user_trace_width 0.1524)
+    (user_trace_width 0.254)
+    (user_trace_width 0.3302)
+    (user_trace_width 0.508)
+    (user_trace_width 0.762)
+    (user_trace_width 1.27)
+    (trace_clearance 0.1524)
+    (zone_clearance 0.508)
+    (zone_45_only no)
+    (trace_min 0.1524)
+    (segment_width 0.1524)
+    (edge_width 0.1524)
+    (via_size 0.6858)
+    (via_drill 0.3302)
+    (via_min_size 0.6858)
+    (via_min_drill 0.3302)
+    (user_via 0.6858 0.3302)
+    (user_via 0.762 0.4064)
+    (user_via 0.8636 0.508)
+    (uvia_size 0.6858)
+    (uvia_drill 0.3302)
+    (uvias_allowed no)
+    (uvia_min_size 0)
+    (uvia_min_drill 0)
+    (pcb_text_width 0.1524)
+    (pcb_text_size 1.016 1.016)
+    (mod_edge_width 0.1524)
+    (mod_text_size 1.016 1.016)
+    (mod_text_width 0.1524)
+    (pad_size 1.524 1.524)
+    (pad_drill 0.762)
+    (pad_to_mask_clearance 0.0508)
+    (solder_mask_min_width 0.1016)
+    (pad_to_paste_clearance -0.0762)
+    (aux_axis_origin 0 0)
+    (visible_elements FFFEDF7D)
+    (pcbplotparams
+      (layerselection 0x310fc_80000001)
+      (usegerberextensions true)
+      (usegerberattributes false)
+      (usegerberadvancedattributes false)
+      (creategerberjobfile false)
+      (excludeedgelayer true)
+      (linewidth 0.100000)
+      (plotframeref false)
+      (viasonmask false)
+      (mode 1)
+      (useauxorigin false)
+      (hpglpennumber 1)
+      (hpglpenspeed 20)
+      (hpglpendiameter 15.000000)
+      (psnegative false)
+      (psa4output false)
+      (plotreference true)
+      (plotvalue true)
+      (plotinvisibletext false)
+      (padsonsilk false)
+      (subtractmaskfromsilk false)
+      (outputformat 1)
+      (mirror false)
+      (drillshape 0)
+      (scaleselection 1)
+      (outputdirectory "gerbers"))
+  )
+
+  (net 0 "")
+
+  (net_class Default "This is the default net class."
+    (clearance 0.1524)
+    (trace_width 0.1524)
+    (via_dia 0.6858)
+    (via_drill 0.3302)
+    (uvia_dia 0.6858)
+    (uvia_drill 0.3302)
+  )
+
+  (gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n5. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n   SOLDER MASK (ANY COLOR) OVER BARE COPPER. \n6. SILK: BOTH SIDES OF THE BOARD SHALL HAVE \n   WHITE SILKSCREEN. DO NOT PLACE SILK OVER BARE COPPER.\n7. FINISH: HASL/ENIG.\n8. MINIMUM TRACE WIDTH - 0.006 INCH.\n   MINIMUM SPACE - 0.006 INCH.\n   MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 113.4872 93.2688) (layer Dwgs.User)
+    (effects (font (size 2.54 2.54) (thickness 0.254)) (justify left))
+  )
+
+)
diff --git a/bldc-controller.pro b/bldc-controller.pro
new file mode 100644
index 0000000..ff5741b
--- /dev/null
+++ b/bldc-controller.pro
@@ -0,0 +1,41 @@
+update=Tue 11 Oct 2016 05:25:07 PM PDT
+version=1
+last_client=kicad
+[cvpcb]
+version=1
+NetIExt=net
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.016000000000
+PcbTextSizeH=1.016000000000
+PcbTextThickness=0.152400000000
+ModuleTextSizeV=1.016000000000
+ModuleTextSizeH=1.016000000000
+ModuleTextSizeThickness=0.152400000000
+SolderMaskClearance=0.003000000000
+SolderMaskMinWidth=0.004000000000
+DrawSegmentWidth=0.152400000000
+BoardOutlineThickness=0.152400000000
+ModuleOutlineThickness=0.152400000000
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=50
+[general]
+version=1
diff --git a/bldc-controller.sch b/bldc-controller.sch
new file mode 100644
index 0000000..25a91ad
--- /dev/null
+++ b/bldc-controller.sch
@@ -0,0 +1,105 @@
+EESchema Schematic File Version 4
+LIBS:bldc-controller-cache
+EELAYER 30 0
+EELAYER END
+$Descr USLetter 11000 8500
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Device:Q_NMOS_DGS Q?
+U 1 1 5DC9FED8
+P 6950 1300
+F 0 "Q?" H 7150 1350 50  0000 L CNN
+F 1 "Q_NMOS_DGS" H 7150 1250 50  0000 L CNN
+F 2 "" H 7150 1400 50  0001 C CNN
+F 3 "~" H 6950 1300 50  0001 C CNN
+	1    6950 1300
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:Q_NMOS_DGS Q?
+U 1 1 5DCA038D
+P 6950 1850
+F 0 "Q?" H 7150 1900 50  0000 L CNN
+F 1 "Q_NMOS_DGS" H 7150 1800 50  0000 L CNN
+F 2 "" H 7150 1950 50  0001 C CNN
+F 3 "~" H 6950 1850 50  0001 C CNN
+	1    6950 1850
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R_Shunt R?
+U 1 1 5DCA0B2B
+P 7050 2400
+F 0 "R?" V 6875 2400 50  0000 C CNN
+F 1 "R_Shunt" V 6950 2400 50  0000 C CNN
+F 2 "" V 6980 2400 50  0001 C CNN
+F 3 "~" H 7050 2400 50  0001 C CNN
+	1    7050 2400
+	-1   0    0    -1  
+$EndComp
+$Comp
+L Device:C_Small C?
+U 1 1 5DCA154B
+P 3300 1700
+F 0 "C?" H 3310 1770 50  0000 L CNN
+F 1 "C_Small" H 3310 1620 50  0000 L CNN
+F 2 "" H 3300 1700 50  0001 C CNN
+F 3 "~" H 3300 1700 50  0001 C CNN
+	1    3300 1700
+	1    0    0    -1  
+$EndComp
+$Comp
+L Connector_Generic:Conn_01x02 J?
+U 1 1 5DCAD005
+P 2500 1550
+F 0 "J?" H 2500 1650 50  0000 C CNN
+F 1 "Conn_01x02" H 2500 1350 50  0000 C CNN
+F 2 "" H 2500 1550 50  0001 C CNN
+F 3 "~" H 2500 1550 50  0001 C CNN
+	1    2500 1550
+	-1   0    0    -1  
+$EndComp
+$Comp
+L Device:C_Small C?
+U 1 1 5DCAFA7B
+P 3700 1700
+F 0 "C?" H 3710 1770 50  0000 L CNN
+F 1 "C_Small" H 3710 1620 50  0000 L CNN
+F 2 "" H 3700 1700 50  0001 C CNN
+F 3 "~" H 3700 1700 50  0001 C CNN
+	1    3700 1700
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:C_Small C?
+U 1 1 5DCAFF60
+P 4050 1700
+F 0 "C?" H 4060 1770 50  0000 L CNN
+F 1 "C_Small" H 4060 1620 50  0000 L CNN
+F 2 "" H 4050 1700 50  0001 C CNN
+F 3 "~" H 4050 1700 50  0001 C CNN
+	1    4050 1700
+	1    0    0    -1  
+$EndComp
+$Comp
+L drv835x:DRV8353RSRGZ U?
+U 1 1 5DCD5043
+P 3100 4550
+F 0 "U?" H 2700 3200 50  0000 L CNN
+F 1 "DRV8353RSRGZ" H 3500 5900 50  0000 R CNN
+F 2 "" H 3100 4550 50  0001 L CNN
+F 3 "" H 3100 4550 50  0001 L CNN
+	1    3100 4550
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/bldc-controller.sch-bak b/bldc-controller.sch-bak
new file mode 100644
index 0000000..0807b87
--- /dev/null
+++ b/bldc-controller.sch-bak
@@ -0,0 +1,94 @@
+EESchema Schematic File Version 4
+LIBS:bldc-controller-cache
+EELAYER 30 0
+EELAYER END
+$Descr USLetter 11000 8500
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Device:Q_NMOS_DGS Q?
+U 1 1 5DC9FED8
+P 6950 1300
+F 0 "Q?" H 7150 1350 50  0000 L CNN
+F 1 "Q_NMOS_DGS" H 7150 1250 50  0000 L CNN
+F 2 "" H 7150 1400 50  0001 C CNN
+F 3 "~" H 6950 1300 50  0001 C CNN
+	1    6950 1300
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:Q_NMOS_DGS Q?
+U 1 1 5DCA038D
+P 6950 1850
+F 0 "Q?" H 7150 1900 50  0000 L CNN
+F 1 "Q_NMOS_DGS" H 7150 1800 50  0000 L CNN
+F 2 "" H 7150 1950 50  0001 C CNN
+F 3 "~" H 6950 1850 50  0001 C CNN
+	1    6950 1850
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R_Shunt R?
+U 1 1 5DCA0B2B
+P 7050 2400
+F 0 "R?" V 6875 2400 50  0000 C CNN
+F 1 "R_Shunt" V 6950 2400 50  0000 C CNN
+F 2 "" V 6980 2400 50  0001 C CNN
+F 3 "~" H 7050 2400 50  0001 C CNN
+	1    7050 2400
+	-1   0    0    -1  
+$EndComp
+$Comp
+L Device:C_Small C?
+U 1 1 5DCA154B
+P 3300 1700
+F 0 "C?" H 3310 1770 50  0000 L CNN
+F 1 "C_Small" H 3310 1620 50  0000 L CNN
+F 2 "" H 3300 1700 50  0001 C CNN
+F 3 "~" H 3300 1700 50  0001 C CNN
+	1    3300 1700
+	1    0    0    -1  
+$EndComp
+$Comp
+L Connector_Generic:Conn_01x02 J?
+U 1 1 5DCAD005
+P 2500 1550
+F 0 "J?" H 2500 1650 50  0000 C CNN
+F 1 "Conn_01x02" H 2500 1350 50  0000 C CNN
+F 2 "" H 2500 1550 50  0001 C CNN
+F 3 "~" H 2500 1550 50  0001 C CNN
+	1    2500 1550
+	-1   0    0    -1  
+$EndComp
+$Comp
+L Device:C_Small C?
+U 1 1 5DCAFA7B
+P 3700 1700
+F 0 "C?" H 3710 1770 50  0000 L CNN
+F 1 "C_Small" H 3710 1620 50  0000 L CNN
+F 2 "" H 3700 1700 50  0001 C CNN
+F 3 "~" H 3700 1700 50  0001 C CNN
+	1    3700 1700
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:C_Small C?
+U 1 1 5DCAFF60
+P 4050 1700
+F 0 "C?" H 4060 1770 50  0000 L CNN
+F 1 "C_Small" H 4060 1620 50  0000 L CNN
+F 2 "" H 4050 1700 50  0001 C CNN
+F 3 "~" H 4050 1700 50  0001 C CNN
+	1    4050 1700
+	1    0    0    -1  
+$EndComp
+$EndSCHEMATC
diff --git a/drv8353.pdf b/drv8353.pdf
new file mode 100644
index 0000000..8143010
Binary files /dev/null and b/drv8353.pdf differ
diff --git a/drv835x.dcm b/drv835x.dcm
new file mode 100644
index 0000000..5f3ed79
--- /dev/null
+++ b/drv835x.dcm
@@ -0,0 +1,3 @@
+EESchema-DOCLIB  Version 2.0
+#
+#End Doc Library
diff --git a/drv835x.lib b/drv835x.lib
new file mode 100644
index 0000000..a61ccac
--- /dev/null
+++ b/drv835x.lib
@@ -0,0 +1,171 @@
+EESchema-LIBRARY Version 2.4
+#encoding utf-8
+#
+# DRV8350HRTV
+#
+DEF DRV8350HRTV U 0 20 Y Y 1 F N
+F0 "U" -400 -950 50 H V L CNN
+F1 "DRV8350HRTV" 400 950 50 H V R CNN
+F2 "" 0 0 50 H I L CNN
+F3 "" 0 0 50 H I L CNN
+DRAW
+S -400 900 400 -900 0 0 10 f
+X EP 0 0 -1000 100 U 50 50 1 1 P
+X CPH 1 -600 800 200 R 50 50 1 1 P
+X GLB 10 -600 -100 200 R 50 50 1 1 O
+X SHB 11 -600 -200 200 R 50 50 1 1 I
+X GHB 12 -600 -300 200 R 50 50 1 1 O
+X GHC 13 -600 -400 200 R 50 50 1 1 O
+X SHC 14 -600 -500 200 R 50 50 1 1 I
+X GLC 15 -600 -600 200 R 50 50 1 1 O
+X SLC 16 -600 -700 200 R 50 50 1 1 I
+X nFAULT 17 600 -700 200 L 50 50 1 1 C
+X MODE 18 600 -600 200 L 50 50 1 1 I
+X IDRIVE 19 600 -500 200 L 50 50 1 1 I
+X VM 2 -600 700 200 R 50 50 1 1 W
+X VDS 20 600 -400 200 L 50 50 1 1 I
+X NC 21 600 -300 200 L 50 50 1 1 N
+X ENABLE 22 600 -200 200 L 50 50 1 1 I
+X INHA 23 600 -100 200 L 50 50 1 1 I
+X INLA 24 600 0 200 L 50 50 1 1 I
+X INHB 25 600 100 200 L 50 50 1 1 I
+X INLB 26 600 200 200 L 50 50 1 1 I
+X INHC 27 600 300 200 L 50 50 1 1 I
+X INLC 28 600 400 200 L 50 50 1 1 I
+X DVDD 29 600 500 200 L 50 50 1 1 W
+X VDRAIN 3 -600 600 200 R 50 50 1 1 I
+X GND 30 600 600 200 L 50 50 1 1 P
+X VGLS 31 600 700 200 L 50 50 1 1 w
+X CPL 32 600 800 200 L 50 50 1 1 P
+X VCP 4 -600 500 200 R 50 50 1 1 W
+X GHA 5 -600 400 200 R 50 50 1 1 O
+X SHA 6 -600 300 200 R 50 50 1 1 I
+X GLA 7 -600 200 200 R 50 50 1 1 O
+X SLA 8 -600 100 200 R 50 50 1 1 I
+X SLB 9 -600 0 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# DRV8353RHRGZ
+#
+DEF DRV8353RHRGZ U 0 20 Y Y 1 F N
+F0 "U" -400 -1350 50 H V L CNN
+F1 "DRV8353RHRGZ" 400 1350 50 H V R CNN
+F2 "" 0 0 50 H I L CNN
+F3 "" 0 0 50 H I L CNN
+DRAW
+S -400 1300 400 -1300 0 0 10 f
+X EP 0 0 -1400 100 U 50 50 1 1 P
+X GND 1 -600 1200 200 R 50 50 1 1 P
+X GLA 10 -600 300 200 R 50 50 1 1 O
+X SPA 11 -600 200 200 R 50 50 1 1 I
+X SNA 12 -600 100 200 R 50 50 1 1 I
+X SNB 13 -600 0 200 R 50 50 1 1 I
+X SPB 14 -600 -100 200 R 50 50 1 1 I
+X GLB 15 -600 -200 200 R 50 50 1 1 O
+X SHB 16 -600 -300 200 R 50 50 1 1 I
+X GHB 17 -600 -400 200 R 50 50 1 1 O
+X GHC 18 -600 -500 200 R 50 50 1 1 O
+X SHC 19 -600 -600 200 R 50 50 1 1 I
+X VGLS 2 -600 1100 200 R 50 50 1 1 W
+X GLC 20 -600 -700 200 R 50 50 1 1 O
+X SPC 21 -600 -800 200 R 50 50 1 1 I
+X SNC 22 -600 -900 200 R 50 50 1 1 I
+X SOC 23 -600 -1000 200 R 50 50 1 1 O
+X SOB 24 -600 -1100 200 R 50 50 1 1 O
+X SOA 25 600 -1100 200 L 50 50 1 1 O
+X VREF 26 600 -1000 200 L 50 50 1 1 W
+X AGND 27 600 -900 200 L 50 50 1 1 P
+X nFAULT 28 600 -800 200 L 50 50 1 1 C
+X MODE 29 600 -700 200 L 50 50 1 1 I
+X CPL 3 -600 1000 200 R 50 50 1 1 P
+X IDRIVE 30 600 -600 200 L 50 50 1 1 I
+X VDS 31 600 -500 200 L 50 50 1 1 I
+X GAIN 32 600 -400 200 L 50 50 1 1 I
+X ENABLE 33 600 -300 200 L 50 50 1 1 I
+X INHA 34 600 -200 200 L 50 50 1 1 I
+X INLA 35 600 -100 200 L 50 50 1 1 I
+X INHB 36 600 0 200 L 50 50 1 1 I
+X INLB 37 600 100 200 L 50 50 1 1 I
+X INHC 38 600 200 200 L 50 50 1 1 I
+X INLC 39 600 300 200 L 50 50 1 1 I
+X CPH 4 -600 900 200 R 50 50 1 1 P
+X DVDD 40 600 400 200 L 50 50 1 1 W
+X DGND 41 600 500 200 L 50 50 1 1 P
+X SW 42 600 600 200 L 50 50 1 1 O
+X VIN 43 600 700 200 L 50 50 1 1 W
+X VCC 44 600 800 200 L 50 50 1 1 w
+X BST 45 600 900 200 L 50 50 1 1 W
+X RCL 46 600 1000 200 L 50 50 1 1 I
+X RT/SD 47 600 1100 200 L 50 50 1 1 I
+X FB 48 600 1200 200 L 50 50 1 1 I
+X VM 5 -600 800 200 R 50 50 1 1 W
+X VDRAIN 6 -600 700 200 R 50 50 1 1 I
+X VCP 7 -600 600 200 R 50 50 1 1 w
+X GHA 8 -600 500 200 R 50 50 1 1 O
+X SHA 9 -600 400 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# DRV8353RSRGZ
+#
+DEF DRV8353RSRGZ U 0 20 Y Y 1 F N
+F0 "U" -400 -1350 50 H V L CNN
+F1 "DRV8353RSRGZ" 400 1350 50 H V R CNN
+F2 "" 0 0 50 H I L CNN
+F3 "" 0 0 50 H I L CNN
+DRAW
+S -400 1300 400 -1300 0 0 10 f
+X EP 0 0 -1400 100 U 50 50 1 1 P
+X GND 1 -600 1200 200 R 50 50 1 1 P
+X GLA 10 -600 300 200 R 50 50 1 1 O
+X SPA 11 -600 200 200 R 50 50 1 1 I
+X SNA 12 -600 100 200 R 50 50 1 1 I
+X SNB 13 -600 0 200 R 50 50 1 1 I
+X SPB 14 -600 -100 200 R 50 50 1 1 I
+X GLB 15 -600 -200 200 R 50 50 1 1 O
+X SHB 16 -600 -300 200 R 50 50 1 1 I
+X GHB 17 -600 -400 200 R 50 50 1 1 O
+X GHC 18 -600 -500 200 R 50 50 1 1 O
+X SHC 19 -600 -600 200 R 50 50 1 1 I
+X VGLS 2 -600 1100 200 R 50 50 1 1 w
+X GLC 20 -600 -700 200 R 50 50 1 1 O
+X SPC 21 -600 -800 200 R 50 50 1 1 I
+X SNC 22 -600 -900 200 R 50 50 1 1 I
+X SOC 23 -600 -1000 200 R 50 50 1 1 O
+X SOB 24 -600 -1100 200 R 50 50 1 1 O
+X SOA 25 600 -1100 200 L 50 50 1 1 O
+X VREF 26 600 -1000 200 L 50 50 1 1 W
+X AGND 27 600 -900 200 L 50 50 1 1 P
+X nFAULT 28 600 -800 200 L 50 50 1 1 C
+X SDO 29 600 -700 200 L 50 50 1 1 C
+X CPL 3 -600 1000 200 R 50 50 1 1 w
+X SDI 30 600 -600 200 L 50 50 1 1 I
+X SCLK 31 600 -500 200 L 50 50 1 1 I
+X nSCS 32 600 -400 200 L 50 50 1 1 I
+X ENABLE 33 600 -300 200 L 50 50 1 1 I
+X INHA 34 600 -200 200 L 50 50 1 1 I
+X INLA 35 600 -100 200 L 50 50 1 1 I
+X INHB 36 600 0 200 L 50 50 1 1 I
+X INLB 37 600 100 200 L 50 50 1 1 I
+X INHC 38 600 200 200 L 50 50 1 1 I
+X INLC 39 600 300 200 L 50 50 1 1 I
+X CPH 4 -600 900 200 R 50 50 1 1 w
+X DVDD 40 600 400 200 L 50 50 1 1 W
+X DGND 41 600 500 200 L 50 50 1 1 P
+X SW 42 600 600 200 L 50 50 1 1 O
+X VIN 43 600 700 200 L 50 50 1 1 W
+X VCC 44 600 800 200 L 50 50 1 1 W
+X BST 45 600 900 200 L 50 50 1 1 I
+X RCL 46 600 1000 200 L 50 50 1 1 I
+X RT/SD 47 600 1100 200 L 50 50 1 1 I
+X FB 48 600 1200 200 L 50 50 1 1 I
+X VM 5 -600 800 200 R 50 50 1 1 W
+X VDRAIN 6 -600 700 200 R 50 50 1 1 I
+X VCP 7 -600 600 200 R 50 50 1 1 w
+X GHA 8 -600 500 200 R 50 50 1 1 O
+X SHA 9 -600 400 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/sym-lib-table b/sym-lib-table
new file mode 100644
index 0000000..9043df3
--- /dev/null
+++ b/sym-lib-table
@@ -0,0 +1,3 @@
+(sym_lib_table
+  (lib (name drv835x)(type Legacy)(uri ${KIPRJMOD}/drv835x.lib)(options "")(descr ""))
+)