diff --git a/rtl/Makefile b/rtl/Makefile
index 9a3f95b..1f5bb0e 100644
--- a/rtl/Makefile
+++ b/rtl/Makefile
@@ -9,7 +9,7 @@ ${FN}_filled.bin: ${FN}.bin
 	python3 -c "import sys; sys.stdout.buffer.write(b'\xff'*${FLASH_SIZE})" > $@;
 	dd if=$< of=$@ conv=notrunc
 
-${FN}.json: ${FN}.v
+${FN}.json: ${FN}.v $(shell find library -type f -name '*.v')
 	./run_yosys.sh ${FN}
 
 ${FN}.asc: ${FN}.json ${FN}.pcf
diff --git a/rtl/bldc.pcf b/rtl/bldc.pcf
index 2fe1a1a..4a67d08 100644
--- a/rtl/bldc.pcf
+++ b/rtl/bldc.pcf
@@ -1,3 +1,4 @@
-set_io --warn-no-port if_int 32
+set_io if_int 32
+set_io dbg_tx 48
 
-set_io --warn-no-port clk 20
+set_io clk 20
diff --git a/rtl/bldc.v b/rtl/bldc.v
index ceb3799..3dddb22 100644
--- a/rtl/bldc.v
+++ b/rtl/bldc.v
@@ -1,13 +1,33 @@
 module bldc (
   input clk,
+  output dbg_tx,
   output if_int
   );
 
+reg [7:0] dbg_buf = 8'hac;
+reg dbg_buf_vld = 1;
+wire dbg_tx_ack;
+
+uart_tx_115200 dbg(
+  .clk_25mhz(clk),
+  .rstn(1'b1),
+  .tx(dbg_tx),
+  .tx_buf(dbg_buf),
+  .tx_vld(dbg_buf_vld),
+  .tx_ack(dbg_tx_ack)
+  );
+
 reg [3:0] tmp = 0;
 assign if_int = tmp[3];
 
 always @(posedge clk) begin
   tmp <= tmp + 1;
+  if (dbg_tx_ack) begin
+    dbg_buf <= dbg_buf + 1;
+    dbg_buf_vld = 1;
+  end else begin
+    dbg_buf_vld = 0;
+  end
 end
 
 endmodule
diff --git a/rtl/library/uart_tx_115200.v b/rtl/library/uart_tx_115200.v
new file mode 100644
index 0000000..6310b58
--- /dev/null
+++ b/rtl/library/uart_tx_115200.v
@@ -0,0 +1,82 @@
+module uart_tx_115200(
+  input clk_25mhz,
+  input rstn,
+  output reg tx,
+  input [7:0] tx_buf,
+  input tx_vld,
+  output tx_ack,
+  );
+
+reg [2:0] bit = 0;
+reg [2:0] bit_next;
+
+reg [7:0] counter = 0;
+reg [7:0] counter_next;
+
+localparam IDLE = 0, START = 1, TX = 2, STOP = 3;
+
+reg [1:0] state = IDLE;
+reg [1:0] state_next;
+
+assign tx_ack = (state == IDLE);
+
+always @* begin
+  case (state)
+    IDLE: tx = 1;
+    START: tx = 0;
+    TX: tx = tx_buf[bit];
+    STOP: tx = 1;
+  endcase
+end
+
+always @* begin
+  state_next = state;
+  counter_next = counter;
+  bit_next = bit;
+
+  if (rstn) begin
+    if (counter == 216) begin
+      counter_next = 0;
+      bit_next = bit + 1;
+    end else begin
+      counter_next = counter + 1;
+    end
+
+    case (state)
+      IDLE: begin
+        if (tx_vld) begin
+          state_next = START;
+          counter_next = 0;
+        end
+      end
+      START: begin
+        if (counter == 216) begin
+          state_next = TX;
+          bit_next = 0;
+        end
+      end
+      TX: begin
+        if ((counter == 216) && (bit == 7)) begin
+          state_next = STOP;
+        end
+      end
+      STOP: begin
+        if (counter == 216) begin
+          state_next = IDLE;
+        end
+      end
+    endcase
+  end else begin
+    state_next = IDLE;
+    counter_next = 0;
+    bit_next = 0;
+  end
+end
+
+always @(posedge clk_25mhz) begin
+    state <= state_next;
+    counter <= counter_next;
+    bit <= bit_next;
+end
+
+endmodule