Add tests Makefile

rtl/library/adc_driver.v

@@ -2,13 +2,13 @@ module adc_driver(
   input clk,
   input rstn,
 
-  input adc_so,
-  output adc_si,
-  output adc_ss,
-  output adc_sck,
+  input so,
+  output si,
+  output ss,
+  output sck,
 
   output [1:0] channel,
-  output [11:0] adc_val,
+  output [11:0] val,
   output vld,
   input ack
 );
@@ -18,7 +18,7 @@ reg [11:0] adc_val_ff = 0;
 reg vld_ff = 0;
 
 assign channel = channel_ff;
-assign adc_val = adc_val_ff;
+assign val = adc_val_ff;
 assign vld = vld_ff;
 
 reg [2:0] sck_strobe = 0;
@@ -47,12 +47,12 @@ reg sck_next;
 reg ss_next;
 reg si_next;
 
-reg adc_si_ff = 1;
-reg adc_ss_ff = 1;
-reg adc_sck_ff = 1;
-assign adc_si = adc_si_ff;
-assign adc_ss = adc_ss_ff;
-assign adc_sck = adc_sck_ff;
+reg si_ff = 1;
+reg ss_ff = 1;
+reg sck_ff = 1;
+assign si = si_ff;
+assign ss = ss_ff;
+assign sck = sck_ff;
 
 wire [15:0] config_word;
 wire config_bit;
@@ -79,14 +79,14 @@ always @* begin
 
   if (rstn) begin
     // latch sck and ss state until the strobe happens
-    si_next = adc_si;
-    ss_next = adc_ss;
-    sck_next = adc_sck;
+    si_next = si;
+    ss_next = ss;
+    sck_next = sck;
 
     if (strobe2) begin
       if (state == CONFIG || state == ADC) begin
           // deassert slave select so it can be triggered on the next frame
-          if (bit_pos == 31 & ~ss_next & ~adc_sck) begin
+          if (bit_pos == 31 & ~ss_next & ~sck) begin
             ss_next = 1;
             //bit_pos_next = 0; // don't need this because it's going to
                                 // overflow
@@ -107,12 +107,12 @@ always @* begin
           bit_pos_next = bit_pos + 1;
 
           // update on the falling edge
-          if (adc_sck) begin
+          if (sck) begin
             si_next = config_bit;
           end
           // switch state on the rising edge after the overflow
           // and reassert ss to start the next frame
-          if (~adc_sck & (bit_pos == 31)) begin
+          if (~sck & (bit_pos == 31)) begin
             //ss_next = 0;
             state_next = ADC;
           end
@@ -125,8 +125,8 @@ always @* begin
 
           // update bit pos state on the rising edge
           // shift in data as well
-          if (~adc_sck) begin
-            so_ff_next = {so_ff[14:0], adc_so};
+          if (~sck) begin
+            so_ff_next = {so_ff[14:0], so};
 
             // after reading the last bit 
             // deassert ss so it can be reasserted on the next rising edge
@@ -150,9 +150,9 @@ always @(posedge clk) begin
   state <= state_next;
   bit_pos <= bit_pos_next;
 
-  adc_sck_ff <= sck_next;
-  adc_ss_ff <= ss_next;
-  adc_si_ff <= si_next;
+  sck_ff <= sck_next;
+  ss_ff <= ss_next;
+  si_ff <= si_next;
   so_ff <= so_ff_next;
 
   // write the data out when write_out is asserted

rtl/tb/.gitignore

@@ -1,2 +1,3 @@
 a.out
 *.vcd
+*_tb

rtl/tb/Makefile

@@ -0,0 +1,9 @@
+tests: test_adc
+
+test_adc: adc_driver_tb.vcd
+
+adc_driver_tb.vcd: ./adc_driver_tb
+	./adc_driver_tb
+	
+adc_driver_tb: adc_driver_tb.v ../library/adc_driver.v
+	iverilog adc_driver_tb.v ../library/adc_driver.v -o adc_driver_tb

rtl/tb/adc_driver_tb.v

@@ -21,13 +21,13 @@ reg ack = 0;
 adc_driver dut(
   .clk(clk),
   .rstn(rstn),
-  .adc_so(adc_so),
-  .adc_si(adc_si),
-  .adc_ss(adc_ss),
-  .adc_sck(adc_sck),
+  .so(adc_so),
+  .si(adc_si),
+  .ss(adc_ss),
+  .sck(adc_sck),
 
   .channel(channel),
-  .adc_val(adc_val),
+  .val(adc_val),
   .vld(vld),
   .ack(ack)
   );