module uart_tx_115200(
  input clk_25mhz,
  input rst,
  output reg tx,
  input [7:0] tx_buf,
  input vld,
  output rdy,
  );

reg [2:0] b = 0;
reg [2:0] b_next;

reg [7:0] counter = 0;
reg [7:0] counter_next;

localparam IDLE = 0, START = 1, TX = 2, STOP = 3;

reg [1:0] state = IDLE;
reg [1:0] state_next;

assign rdy = (state == IDLE);

always @* begin
  case (state)
    IDLE: tx = 1;
    START: tx = 0;
    TX: tx = tx_buf[b];
    STOP: tx = 1;
  endcase
end

always @* begin
  state_next = state;
  counter_next = counter;
  b_next = b;

  if (~rst) begin
    if (counter == 216) begin
      counter_next = 0;
      b_next = b + 1;
    end else begin
      counter_next = counter + 1;
    end

    case (state)
      IDLE: begin
        if (vld) begin
          state_next = START;
          counter_next = 0;
        end
      end
      START: begin
        if (counter == 216) begin
          state_next = TX;
          b_next = 0;
        end
      end
      TX: begin
        if ((counter == 216) && (b == 7)) begin
          state_next = STOP;
        end
      end
      STOP: begin
        if (counter == 216) begin
          state_next = IDLE;
        end
      end
    endcase
  end else begin
    state_next = IDLE;
    counter_next = 0;
    b_next = 0;
  end
end

always @(posedge clk_25mhz) begin
    state <= state_next;
    counter <= counter_next;
    b <= b_next;
end

endmodule
