module bldc (
  input clk,
  output dbg_tx,
  output if_int
  );

reg [7:0] dbg_buf = 8'hac;
reg dbg_buf_vld = 1;
wire dbg_tx_ack;

uart_tx_115200 dbg(
  .clk_25mhz(clk),
  .rstn(1'b1),
  .tx(dbg_tx),
  .tx_buf(dbg_buf),
  .tx_vld(dbg_buf_vld),
  .tx_ack(dbg_tx_ack)
  );

reg [3:0] tmp = 0;
assign if_int = tmp[3];

always @(posedge clk) begin
  tmp <= tmp + 1;
  if (dbg_tx_ack) begin
    dbg_buf <= dbg_buf + 1;
    dbg_buf_vld = 1;
  end else begin
    dbg_buf_vld = 0;
  end
end

endmodule
