kelvin
/
bfu520-test-amplifier
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Layout almost done TODO silkscreen cleanup TODO via stitching

This commit is contained in:
Kelvin Ly 2019-07-13 01:01:57 -04:00
parent 8c80fbeda1
commit 028f1675ae
8 changed files with 74569 additions and 363 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

71234
pcb/iss-lna/fp-info-cache
View File

File diff suppressed because it is too large Load Diff

65
pcb/iss-lna/iss-lna.bak
View File

@ -161,12 +161,12 @@ Wire Wire Line
$Comp
L power:GND #PWR013
U 1 1 5D258DC3
P 6250 5000
F 0 "#PWR013" H 6250 4750 50 0001 C CNN
F 1 "GND" H 6250 4850 50 0000 C CNN
F 2 "" H 6250 5000 50 0001 C CNN
F 3 "" H 6250 5000 50 0001 C CNN
1 6250 5000
P 6450 5400
F 0 "#PWR013" H 6450 5150 50 0001 C CNN
F 1 "GND" H 6450 5250 50 0000 C CNN
F 2 "" H 6450 5400 50 0001 C CNN
F 3 "" H 6450 5400 50 0001 C CNN
1 6450 5400
1 0 0 -1
$EndComp
$Comp
@ -720,8 +720,9 @@ U 1 1 5D37642F
P 9700 3050
F 0 "D1" H 9700 3150 50 0000 C CNN
F 1 "LED" H 9700 2950 50 0000 C CNN
F 2 "" H 9700 3050 50 0001 C CNN
F 2 "LED_SMD:LED_0805_2012Metric" H 9700 3050 50 0001 C CNN
F 3 "~" H 9700 3050 50 0001 C CNN
F 4 " 743-IN-S85ATG " H 9700 3050 50 0001 C CNN "Mouser"
1 9700 3050
0 -1 -1 0
$EndComp
@ -773,8 +774,6 @@ Wire Wire Line
Wire Wire Line
6350 4750 6250 4750
Connection ~ 6250 4750
Wire Wire Line
6250 4750 6250 5000
$Comp
L Connector:Conn_Coaxial J3
U 1 1 5D3AC327
@ -942,4 +941,52 @@ Wire Wire Line
7450 1900 7450 1750
Wire Wire Line
7450 1750 7300 1750
$Comp
L Device:C_Small C13
U 1 1 5D2BD105
P 6450 5200
F 0 "C13" H 6460 5270 50 0000 L CNN
F 1 "470 pF" H 6460 5120 50 0000 L CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 6450 5200 50 0001 C CNN
F 3 "~" H 6450 5200 50 0001 C CNN
1 6450 5200
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R12
U 1 1 5D2F8481
P 6250 5200
F 0 "R12" H 6280 5220 50 0000 L CNN
F 1 "0R" H 6280 5160 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 6250 5200 50 0001 C CNN
F 3 "~" H 6250 5200 50 0001 C CNN
1 6250 5200
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0101
U 1 1 5D306043
P 6250 5400
F 0 "#PWR0101" H 6250 5150 50 0001 C CNN
F 1 "GND" H 6250 5250 50 0000 C CNN
F 2 "" H 6250 5400 50 0001 C CNN
F 3 "" H 6250 5400 50 0001 C CNN
1 6250 5400
1 0 0 -1
$EndComp
Wire Wire Line
6250 5400 6250 5300
Wire Wire Line
6250 4750 6250 5000
Wire Wire Line
6250 5000 6450 5000
Wire Wire Line
6450 5000 6450 5100
Connection ~ 6250 5000
Wire Wire Line
6250 5000 6250 5100
Wire Wire Line
6450 5300 6450 5400
Text Label 9700 2750 0 50 ~ 0
VCC
$EndSCHEMATC

1239
pcb/iss-lna/iss-lna.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

2018
pcb/iss-lna/iss-lna.kicad_pcb-bak
View File

File diff suppressed because it is too large Load Diff

262
pcb/iss-lna/iss-lna.pro
View File

@ -1,29 +1,10 @@
update=22/05/2015 07:44:53
update=Fri 12 Jul 2019 01:38:12 PM EDT
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
@ -31,3 +12,244 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.16
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.16
TrackWidth2=0.16
TrackWidth3=0.2
TrackWidth4=0.25
TrackWidth5=0.3
TrackWidth6=0.8492
TrackWidth7=1.4444
ViaDiameter1=0.69
ViaDrill1=0.33
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.16
TrackWidth=0.16
ViaDiameter=0.69
ViaDrill=0.33
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=RF1
Clearance=0.16
TrackWidth=0.849
ViaDiameter=0.69
ViaDrill=0.33
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

66
pcb/iss-lna/iss-lna.sch
View File

@ -20,7 +20,7 @@ U 1 1 5D244E7D
P 9050 4050
F 0 "J4" H 9060 4170 50 0000 C CNN
F 1 "SMA" V 9165 4050 50 0000 C CNN
F 2 "iss_lna:142-0701-801" H 9050 4050 50 0001 C CNN
F 2 "iss_lna:142-0701-801-with-taper" H 9050 4050 50 0001 C CNN
F 3 " ~" H 9050 4050 50 0001 C CNN
F 4 " 530-142-0701-801 " H 9050 4050 50 0001 C CNN "Mouser"
1 9050 4050
@ -32,7 +32,7 @@ U 1 1 5D24503E
P 1400 4400
F 0 "J1" H 1410 4520 50 0000 C CNN
F 1 "SMA" V 1515 4400 50 0000 C CNN
F 2 "iss_lna:142-0701-801" H 1400 4400 50 0001 C CNN
F 2 "iss_lna:142-0701-801-with-taper" H 1400 4400 50 0001 C CNN
F 3 " ~" H 1400 4400 50 0001 C CNN
F 4 " 530-142-0701-801 " H 1400 4400 50 0001 C CNN "Mouser"
1 1400 4400
@ -161,12 +161,12 @@ Wire Wire Line
$Comp
L power:GND #PWR013
U 1 1 5D258DC3
P 6250 5000
F 0 "#PWR013" H 6250 4750 50 0001 C CNN
F 1 "GND" H 6250 4850 50 0000 C CNN
F 2 "" H 6250 5000 50 0001 C CNN
F 3 "" H 6250 5000 50 0001 C CNN
1 6250 5000
P 6450 5400
F 0 "#PWR013" H 6450 5150 50 0001 C CNN
F 1 "GND" H 6450 5250 50 0000 C CNN
F 2 "" H 6450 5400 50 0001 C CNN
F 3 "" H 6450 5400 50 0001 C CNN
1 6450 5400
1 0 0 -1
$EndComp
$Comp
@ -774,8 +774,6 @@ Wire Wire Line
Wire Wire Line
6350 4750 6250 4750
Connection ~ 6250 4750
Wire Wire Line
6250 4750 6250 5000
$Comp
L Connector:Conn_Coaxial J3
U 1 1 5D3AC327
@ -943,4 +941,52 @@ Wire Wire Line
7450 1900 7450 1750
Wire Wire Line
7450 1750 7300 1750
$Comp
L Device:C_Small C13
U 1 1 5D2BD105
P 6450 5200
F 0 "C13" H 6460 5270 50 0000 L CNN
F 1 "470 pF" H 6460 5120 50 0000 L CNN
F 2 "Capacitor_SMD:C_0402_1005Metric" H 6450 5200 50 0001 C CNN
F 3 "~" H 6450 5200 50 0001 C CNN
1 6450 5200
1 0 0 -1
$EndComp
$Comp
L Device:R_Small R12
U 1 1 5D2F8481
P 6250 5200
F 0 "R12" H 6280 5220 50 0000 L CNN
F 1 "0R" H 6280 5160 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" H 6250 5200 50 0001 C CNN
F 3 "~" H 6250 5200 50 0001 C CNN
1 6250 5200
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR0101
U 1 1 5D306043
P 6250 5400
F 0 "#PWR0101" H 6250 5150 50 0001 C CNN
F 1 "GND" H 6250 5250 50 0000 C CNN
F 2 "" H 6250 5400 50 0001 C CNN
F 3 "" H 6250 5400 50 0001 C CNN
1 6250 5400
1 0 0 -1
$EndComp
Wire Wire Line
6250 5400 6250 5300
Wire Wire Line
6250 4750 6250 5000
Wire Wire Line
6250 5000 6450 5000
Wire Wire Line
6450 5000 6450 5100
Connection ~ 6250 5000
Wire Wire Line
6250 5000 6250 5100
Wire Wire Line
6450 5300 6450 5400
Text Label 9700 2750 0 50 ~ 0
VCC
$EndSCHEMATC

44
pcb/iss-lna/iss_lna.pretty/142-0701-801-with-taper.kicad_mod Normal file
View File

@ -0,0 +1,44 @@
(module 142-0701-801-with-taper (layer F.Cu) (tedit 5D29649C)
(fp_text reference REF** (at 6.52 2.46 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 142-0701-801-with-taper (at 6.7 5.65 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -5.6 0) (end 5.6 0) (layer F.Fab) (width 0.12))
(pad 2 smd rect (at 4.3815 2.665) (size 2.413 4.83) (layers B.Cu F.Paste F.Mask))
(pad 2 smd rect (at -4.3815 2.65) (size 2.413 4.83) (layers B.Cu F.Paste F.Mask))
(pad 2 thru_hole circle (at 4.3815 5.969) (size 0.9652 0.9652) (drill 0.4572) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at -4.3815 5.969) (size 0.9652 0.9652) (drill 0.4572) (layers *.Cu *.Mask))
(pad 1 smd rect (at 0 5.3721) (size 2.6162 0.254) (layers F.Cu F.Paste F.Mask))
(pad 1 smd trapezoid (at 0 5.16255) (size 2.4511 0.1651) (rect_delta 0 0.1651 ) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -4.3815 2.665) (size 2.413 4.83) (layers F.Cu F.Paste F.Mask))
(pad 1 smd rect (at 0 2.665) (size 2.286 4.83) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 4.3815 2.665) (size 2.413 4.83) (layers F.Cu F.Paste F.Mask))
(pad 2 smd custom (at -3.04 9.83) (size 0.9652 0.9652) (layers F.Cu)
(zone_connect 2)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy -0.14 -4.75) (xy 0.38 -4.34) (xy 0.52 -4.17) (xy 0.68 -4.01) (xy 0.91 -3.7)
(xy 1.27 -3.045) (xy 1.73 -1.77) (xy 2.44 0.79) (xy -2.54 0.79) (xy -2.54 -4.75)
) (width 0))
))
(pad 1 smd custom (at -0.04 7.28) (size 0.9652 0.9652) (layers F.Cu F.Paste F.Mask)
(zone_connect 0)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy -0.83 0.78) (xy -1.05 -0.5) (xy -1.16 -1.14) (xy -1.215 -1.46) (xy -1.27 -1.78)
(xy 1.35 -1.78) (xy 0.47 3.34) (xy -0.39 3.34)) (width 0))
))
(pad 2 smd custom (at 3.91 8.81) (size 0.9652 0.9652) (layers F.Cu)
(zone_connect 2)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy -0.72 -3.73) (xy -1.24 -3.32) (xy -1.38 -3.15) (xy -1.54 -2.99) (xy -1.77 -2.68)
(xy -2.13 -2.025) (xy -2.59 -0.75) (xy -3.3 1.81) (xy 1.68 1.81) (xy 1.68 -3.73)
) (width 0))
))
)

4
pcb/iss-lna/iss_lna.pretty/142-0701-801.kicad_mod
View File

@ -1,4 +1,4 @@
(module 142-0701-801 (layer F.Cu) (tedit 5D280189)
(module 142-0701-801 (layer F.Cu) (tedit 5D290825)
(fp_text reference REF** (at -0.05 6.4) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
@ -13,4 +13,6 @@
(pad 1 smd rect (at 0 5.3721) (size 2.6162 0.254) (layers F.Cu F.Paste F.Mask))
(pad 2 thru_hole circle (at -4.3815 5.969) (size 0.9652 0.9652) (drill 0.4572) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at 4.3815 5.969) (size 0.9652 0.9652) (drill 0.4572) (layers *.Cu *.Mask))
(pad 2 smd rect (at -4.3815 2.65) (size 2.413 4.83) (layers B.Cu F.Paste F.Mask))
(pad 2 smd rect (at 4.3815 2.665) (size 2.413 4.83) (layers B.Cu F.Paste F.Mask))
)